Re: [PATCH v3] arm64: dts: ti: k3-am65: Change #address-cells and #size-cells of interconnect to 2

[Tero Kristo]

On 05/09/18 16:40, Nishanth Menon wrote:
> On 11:17-20180905, Kishon Vijay Abraham I wrote:
> > AM65 has two PCIe controllers and each PCIe controller has '2' address
> > spaces one within the 4GB address space of the SoC and the other above
> > the 4GB address space of the SoC (cbass_main) in addition to the
> > register space. The size of the address space above the 4GB SoC address
> > space is 4GB. These address ranges will be used by CPU/DMA to access
> > the PCIe address space. In order to represent the address space above
> > the 4GB SoC address space and to represent the size of this address
> > space as 4GB, change address-cells and size-cells of interconnect to 2.
> >
> > Since OSPI has similar need in MCU Domain Memory Map, change
> > address-cells and size-cells of cbass_mcu interconnect also to 2.
> >
> > Fixes: ea47eed33a3fe3d919 ("arm64: dts: ti: Add Support for AM654 SoC")
> > Signed-off-by: Kishon Vijay Abraham I <kishon@xxxxxx>
> > Acked-by: Tony Lindgren <tony@xxxxxxxxxxx>
> > Acked-by: Vignesh R <vigneshr@xxxxxx>
> > ---
> > Changes from v2:
> > Added Fixes tag.
>
> Thanks.
> Acked-by: Nishanth Menon <nm@xxxxxx>
>
> Tero: Could we take this for v4.20 ? While this is a bug fix, I think
> it might be better in v4.20 window since it will help provide a clean merge
> of follow on nodes.

Yes, queuing up for 4.20, thanks.

-Tero
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