Re: [PATCH] ACPI/PPTT: Handle architecturally unknown cache types

[Jeffrey Hugo]

On 9/12/2018 9:39 AM, Jeremy Linton wrote:
> Hi,
>
>
> On 09/12/2018 09:41 AM, Jeffrey Hugo wrote:
> > The HW designers have indicated that there is no sane way to provide 
> > sets/ways information to software, even on an informational basis (ie 
> > not for cache maintenance, but for performance optimizations). 
> > Therefore the firmware will not provide this information because it 
> > will be wrong.
> >
> > So, therefore, we should still be able to tell the user that a cache 
> > exists at the relevant level, and what size it is. On the concerned 
> > system, we cannot do that currently.
>
> Ok, so set the fields to zero in firmware node, and mark them valid.

Is that what the PPTT spec says to do?

> That logically says that there isn't any set/way information for the 
> cache (which implies direct mapped).

Making inferences such as that have gotten folks into trouble when 
interpreting other specs.  Unfortunately I am not allowed to detail more 
about this specific system, however implying that the affected cache(s) 
are direct mapped is incorrect.  Officially, what you have is a cache or 
multiple caches at certain levels that have a specified size.  You can 
make no inferences about the exact behavior or implementation of the 
cache beyond what FW explicitly provides.  I'm not particularly a fan of 
it, but its what I have to deal with.

--
Jeffrey Hugo
Qualcomm Datacenter Technologies as an affiliate of Qualcomm 
Technologies, Inc.
Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.