Re: [PATCH] ia64: fix barrier placement for write* / dma mapping

[Sinan Kaya]

On 8/1/2018 12:29 AM, Christoph Hellwig wrote:
> > I asked this question to Tony Luck before. If I remember right,
> > his answer was:
> >
> > CPU guarantees outstanding writes to be flushed when a register write
> > instruction is executed and an additional barrier instruction is not
> > needed.
> That would be great.  It still doesn't explain the barriers in the
> dma sync routines.  Those have been there since the following commit
> in the history tree:

Yeah, I'll let Tony confirm my understanding.