[PATCH 1/8] ARM: dts: artpec: disable Accelerator Coherency Port

From: Niklas Cassel
Date: Tue Feb 20 2018 - 12:01:29 EST


Accesses via 0x80000000 go through the ACP instead of using the DDR
directly.

Unfortunately the ACP has proven to be the cause of complete system
hangs. Disabling the ACP makes these problems go away.

Signed-off-by: Niklas Cassel <niklas.cassel@xxxxxxxx>
---
arch/arm/boot/dts/artpec6.dtsi | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/artpec6.dtsi b/arch/arm/boot/dts/artpec6.dtsi
index 2ed11773048d..d9776a97d8ff 100644
--- a/arch/arm/boot/dts/artpec6.dtsi
+++ b/arch/arm/boot/dts/artpec6.dtsi
@@ -185,8 +185,7 @@
#address-cells = <0x1>;
#size-cells = <0x1>;
ranges;
- dma-ranges = <0x80000000 0x00000000 0x40000000>;
- dma-coherent;
+ dma-ranges;

ethernet: ethernet@f8010000 {
clock-names = "phy_ref_clk", "apb_pclk";
--
2.14.2