[PATCH 2/8] x86/msr: add definitions for indirect branch predictor MSRs

[Paolo Bonzini]

These MSRs are available if the CPU features SPEC_CTRL
(CPUID(EAX=7,ECX=0).EDX[26]) is present.  The PRED_CMD MSR
is also available if the CPU feature IBPB_SUPPORT
(CPUID(EAX=0x80000008).EBX[12]) is present.

KVM will soon start using PRED_CMD and will make SPEC_CTRL
available to guests.

Reviewed-by: Liran Alon <liran.alon@xxxxxxxxxx>
Signed-off-by: Paolo Bonzini <pbonzini@xxxxxxxxxx>
---
 arch/x86/include/asm/msr-index.h | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 03ffde6217d0..828a03425571 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -464,8 +464,15 @@
 #define MSR_SMI_COUNT			0x00000034
 #define MSR_IA32_FEATURE_CONTROL        0x0000003a
 #define MSR_IA32_TSC_ADJUST             0x0000003b
-#define MSR_IA32_BNDCFGS		0x00000d90
 
+#define MSR_IA32_SPEC_CTRL		0x00000048
+#define SPEC_CTRL_FEATURE_DISABLE_IBRS	(0 << 0)
+#define SPEC_CTRL_FEATURE_ENABLE_IBRS	(1 << 0)
+
+#define MSR_IA32_PRED_CMD		0x00000049
+#define PRED_CMD_IBPB			(1UL << 0)
+
+#define MSR_IA32_BNDCFGS		0x00000d90
 #define MSR_IA32_BNDCFGS_RSVD		0x00000ffc
 
 #define MSR_IA32_XSS			0x00000da0
-- 
1.8.3.1