[PATCH v3 13/17] bindings: PCI: artpec: Add support for endpoint mode

From: Niklas Cassel
Date: Tue Oct 31 2017 - 18:44:52 EST


Signed-off-by: Niklas Cassel <niklas.cassel@xxxxxxxx>
Acked-by: Rob Herring <robh@xxxxxxxxxx>
---
V3:
* No change.

Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt b/Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt
index 4e4aee4439ea..33eef7ae5a23 100644
--- a/Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt
@@ -4,7 +4,8 @@ This PCIe host controller is based on the Synopsys DesignWare PCIe IP
and thus inherits all the common properties defined in designware-pcie.txt.

Required properties:
-- compatible: "axis,artpec6-pcie", "snps,dw-pcie"
+- compatible: "axis,artpec6-pcie", "snps,dw-pcie" for ARTPEC-6 in RC mode;
+ "axis,artpec6-pcie-ep", "snps,dw-pcie" for ARTPEC-6 in EP mode;
- reg: base addresses and lengths of the PCIe controller (DBI),
the PHY controller, and configuration address space.
- reg-names: Must include the following entries:
--
2.14.2