[PATCH 1/3] staging: pi433: Style fix - align block comments

From: Derek Robson
Date: Fri Jul 21 2017 - 23:51:06 EST

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Fixed the alignment of block comments
Found using checkpatch

Signed-off-by: Derek Robson <robsonde@xxxxxxxxx>
---
drivers/staging/pi433/pi433_if.c | 38 +++--
drivers/staging/pi433/rf69.c | 10 +-
drivers/staging/pi433/rf69_registers.h | 280 ++++++++++++++++-----------------
3 files changed, 169 insertions(+), 159 deletions(-)

diff --git a/drivers/staging/pi433/pi433_if.c b/drivers/staging/pi433/pi433_if.c
index 1bc478a7f49e..9cdebe93657c 100644
--- a/drivers/staging/pi433/pi433_if.c
+++ b/drivers/staging/pi433/pi433_if.c
@@ -67,9 +67,11 @@ static DEFINE_MUTEX(minor_lock); /* Protect idr accesses */
static struct class *pi433_class; /* mainly for udev to create /dev/pi433 */

/* tx config is instance specific
- so with each open a new tx config struct is needed */
+ * so with each open a new tx config struct is needed
+ */
/* rx config is device specific
- so we have just one rx config, ebedded in device struct */
+ * so we have just one rx config, ebedded in device struct
+ */
struct pi433_device {
/* device handling related values */
dev_t devt;
@@ -486,9 +488,10 @@ pi433_tx_thread(void *data)
return 0;

/* get data from fifo in the following order:
- - tx_cfg
- - size of message
- - message */
+ * - tx_cfg
+ * - size of message
+ * - message
+ */
mutex_lock(&device->tx_fifo_lock);

retval = kfifo_out(&device->tx_fifo, &tx_cfg, sizeof(tx_cfg));
@@ -537,23 +540,26 @@ pi433_tx_thread(void *data)
mutex_unlock(&device->tx_fifo_lock);

/* if rx is active, we need to interrupt the waiting for
- incoming telegrams, to be able to send something.
- We are only allowed, if currently no reception takes
- place otherwise we need to wait for the incoming telegram
- to finish */
+ * incoming telegrams, to be able to send something.
+ * We are only allowed, if currently no reception takes
+ * place otherwise we need to wait for the incoming telegram
+ * to finish
+ */
wait_event_interruptible(device->tx_wait_queue,
!device->rx_active ||
device->interrupt_rx_allowed == true);

/* prevent race conditions
- irq will be reenabled after tx config is set */
+ * irq will be reenabled after tx config is set
+ */
disable_irq(device->irq_num[DIO0]);
device->tx_active = true;

if (device->rx_active && rx_interrupted == false)
{
/* rx is currently waiting for a telegram;
- we need to set the radio module to standby */
+ * we need to set the radio module to standby
+ */
SET_CHECKED(rf69_set_mode(device->spi, standby));
rx_interrupted = true;
}
@@ -712,9 +718,10 @@ pi433_write(struct file *filp, const char __user *buf,
return -EMSGSIZE;

/* write the following sequence into fifo:
- - tx_cfg
- - size of message
- - message */
+ * - tx_cfg
+ * - size of message
+ * - message
+ */
mutex_lock(&device->tx_fifo_lock);
retval = kfifo_in(&device->tx_fifo, &instance->tx_cfg, sizeof(instance->tx_cfg));
if ( retval != sizeof(instance->tx_cfg) )
@@ -1269,7 +1276,8 @@ static int __init pi433_init(void)
int status;

/* If MAX_MSG_SIZE is smaller then FIFO_SIZE, the driver won't
- work stable - risk of buffer overflow */
+ * work stable - risk of buffer overflow
+ */
if (MAX_MSG_SIZE < FIFO_SIZE)
return -EINVAL;

diff --git a/drivers/staging/pi433/rf69.c b/drivers/staging/pi433/rf69.c
index e391ce777bc7..7f4db9a1f39a 100644
--- a/drivers/staging/pi433/rf69.c
+++ b/drivers/staging/pi433/rf69.c
@@ -939,8 +939,9 @@ u8 rf69_read_reg(struct spi_device *spi, u8 addr)
#ifdef DEBUG_VALUES
if (retval < 0)
/* should never happen, since we already checked,
- that module is connected. Therefore no error
- handling, just an optional error message... */
+ * that module is connected. Therefore no error
+ * handling, just an optional error message...
+ */
dev_dbg(&spi->dev, "read 0x%x FAILED\n",
addr);
else
@@ -965,8 +966,9 @@ int rf69_write_reg(struct spi_device *spi, u8 addr, u8 value)
#ifdef DEBUG_VALUES
if (retval < 0)
/* should never happen, since we already checked,
- that module is connected. Therefore no error
- handling, just an optional error message... */
+ * that module is connected. Therefore no error
+ * handling, just an optional error message...
+ */
dev_dbg(&spi->dev, "write 0x%x to 0x%x FAILED\n",
value,
addr);
diff --git a/drivers/staging/pi433/rf69_registers.h b/drivers/staging/pi433/rf69_registers.h
index d0c4992b0778..6335d42142fe 100644
--- a/drivers/staging/pi433/rf69_registers.h
+++ b/drivers/staging/pi433/rf69_registers.h
@@ -143,44 +143,44 @@
#define FDEVMASB_MASK 0x3f

/*
-// RegOsc1
-#define OSC1_RCCAL_START 0x80
-#define OSC1_RCCAL_DONE 0x40
-
-// RegLowBat
-#define LOWBAT_MONITOR 0x10
-#define LOWBAT_ON 0x08
-#define LOWBAT_OFF 0x00 // Default
-
-#define LOWBAT_TRIM_1695 0x00
-#define LOWBAT_TRIM_1764 0x01
-#define LOWBAT_TRIM_1835 0x02 // Default
-#define LOWBAT_TRIM_1905 0x03
-#define LOWBAT_TRIM_1976 0x04
-#define LOWBAT_TRIM_2045 0x05
-#define LOWBAT_TRIM_2116 0x06
-#define LOWBAT_TRIM_2185 0x07
-
-
-// RegListen1
-#define LISTEN1_RESOL_64 0x50
-#define LISTEN1_RESOL_4100 0xA0 // Default
-#define LISTEN1_RESOL_262000 0xF0
-
-#define LISTEN1_CRITERIA_RSSI 0x00 // Default
-#define LISTEN1_CRITERIA_RSSIANDSYNC 0x08
-
-#define LISTEN1_END_00 0x00
-#define LISTEN1_END_01 0x02 // Default
-#define LISTEN1_END_10 0x04
-
-
-// RegListen2
-#define LISTEN2_COEFIDLE_VALUE 0xF5 // Default
-
-// RegListen3
-#define LISTEN3_COEFRX_VALUE 0x20 // Default
-*/
+ * // RegOsc1
+ * #define OSC1_RCCAL_START 0x80
+ * #define OSC1_RCCAL_DONE 0x40
+ *
+ * // RegLowBat
+ * #define LOWBAT_MONITOR 0x10
+ * #define LOWBAT_ON 0x08
+ * #define LOWBAT_OFF 0x00 // Default
+ *
+ * #define LOWBAT_TRIM_1695 0x00
+ * #define LOWBAT_TRIM_1764 0x01
+ * #define LOWBAT_TRIM_1835 0x02 // Default
+ * #define LOWBAT_TRIM_1905 0x03
+ * #define LOWBAT_TRIM_1976 0x04
+ * #define LOWBAT_TRIM_2045 0x05
+ * #define LOWBAT_TRIM_2116 0x06
+ * #define LOWBAT_TRIM_2185 0x07
+ *
+ *
+ * // RegListen1
+ * #define LISTEN1_RESOL_64 0x50
+ * #define LISTEN1_RESOL_4100 0xA0 // Default
+ * #define LISTEN1_RESOL_262000 0xF0
+ *
+ * #define LISTEN1_CRITERIA_RSSI 0x00 // Default
+ * #define LISTEN1_CRITERIA_RSSIANDSYNC 0x08
+ *
+ * #define LISTEN1_END_00 0x00
+ * #define LISTEN1_END_01 0x02 // Default
+ * #define LISTEN1_END_10 0x04
+ *
+ *
+ * // RegListen2
+ * #define LISTEN2_COEFIDLE_VALUE 0xF5 // Default
+ *
+ * // RegListen3
+ * #define LISTEN3_COEFRX_VALUE 0x20 // Default
+ */

// RegPaLevel
#define MASK_PALEVEL_PA0 0x80
@@ -211,27 +211,27 @@
#define MASK_PARAMP 0x0F

/*
-// RegOcp
-#define OCP_OFF 0x0F
-#define OCP_ON 0x1A // Default
-
-#define OCP_TRIM_45 0x00
-#define OCP_TRIM_50 0x01
-#define OCP_TRIM_55 0x02
-#define OCP_TRIM_60 0x03
-#define OCP_TRIM_65 0x04
-#define OCP_TRIM_70 0x05
-#define OCP_TRIM_75 0x06
-#define OCP_TRIM_80 0x07
-#define OCP_TRIM_85 0x08
-#define OCP_TRIM_90 0x09
-#define OCP_TRIM_95 0x0A
-#define OCP_TRIM_100 0x0B // Default
-#define OCP_TRIM_105 0x0C
-#define OCP_TRIM_110 0x0D
-#define OCP_TRIM_115 0x0E
-#define OCP_TRIM_120 0x0F
-*/
+ * // RegOcp
+ * #define OCP_OFF 0x0F
+ * #define OCP_ON 0x1A // Default
+ *
+ * #define OCP_TRIM_45 0x00
+ * #define OCP_TRIM_50 0x01
+ * #define OCP_TRIM_55 0x02
+ * #define OCP_TRIM_60 0x03
+ * #define OCP_TRIM_65 0x04
+ * #define OCP_TRIM_70 0x05
+ * #define OCP_TRIM_75 0x06
+ * #define OCP_TRIM_80 0x07
+ * #define OCP_TRIM_85 0x08
+ * #define OCP_TRIM_90 0x09
+ * #define OCP_TRIM_95 0x0A
+ * #define OCP_TRIM_100 0x0B // Default
+ * #define OCP_TRIM_105 0x0C
+ * #define OCP_TRIM_110 0x0D
+ * #define OCP_TRIM_115 0x0E
+ * #define OCP_TRIM_120 0x0F
+ */

/* RegLna (0x18) */
#define MASK_LNA_ZIN 0x80
@@ -294,32 +294,32 @@
#define OOKPEAK_THRESHDEC_16_TIMES 0x07

/*
-// RegOokAvg
-#define OOKAVG_AVERAGETHRESHFILT_00 0x00
-#define OOKAVG_AVERAGETHRESHFILT_01 0x40
-#define OOKAVG_AVERAGETHRESHFILT_10 0x80 // Default
-#define OOKAVG_AVERAGETHRESHFILT_11 0xC0
-
-
-// RegAfcFei
-#define AFCFEI_FEI_DONE 0x40
-#define AFCFEI_FEI_START 0x20
-#define AFCFEI_AFC_DONE 0x10
-#define AFCFEI_AFCAUTOCLEAR_ON 0x08
-#define AFCFEI_AFCAUTOCLEAR_OFF 0x00 // Default
-
-#define AFCFEI_AFCAUTO_ON 0x04
-#define AFCFEI_AFCAUTO_OFF 0x00 // Default
-
-#define AFCFEI_AFC_CLEAR 0x02
-#define AFCFEI_AFC_START 0x01
-
-// RegRssiConfig
-#define RSSI_FASTRX_ON 0x08
-#define RSSI_FASTRX_OFF 0x00 // Default
-#define RSSI_DONE 0x02
-#define RSSI_START 0x01
-*/
+ * // RegOokAvg
+ * #define OOKAVG_AVERAGETHRESHFILT_00 0x00
+ * #define OOKAVG_AVERAGETHRESHFILT_01 0x40
+ * #define OOKAVG_AVERAGETHRESHFILT_10 0x80 // Default
+ * #define OOKAVG_AVERAGETHRESHFILT_11 0xC0
+ *
+ *
+ * // RegAfcFei
+ * #define AFCFEI_FEI_DONE 0x40
+ * #define AFCFEI_FEI_START 0x20
+ * #define AFCFEI_AFC_DONE 0x10
+ * #define AFCFEI_AFCAUTOCLEAR_ON 0x08
+ * #define AFCFEI_AFCAUTOCLEAR_OFF 0x00 // Default
+ *
+ * #define AFCFEI_AFCAUTO_ON 0x04
+ * #define AFCFEI_AFCAUTO_OFF 0x00 // Default
+ *
+ * #define AFCFEI_AFC_CLEAR 0x02
+ * #define AFCFEI_AFC_START 0x01
+ *
+ * // RegRssiConfig
+ * #define RSSI_FASTRX_ON 0x08
+ * #define RSSI_FASTRX_OFF 0x00 // Default
+ * #define RSSI_DONE 0x02
+ * #define RSSI_START 0x01
+ */

/* RegDioMapping1 */
#define MASK_DIO0 0xC0
@@ -422,66 +422,66 @@
#define PACKETCONFIG1_ADDRESSFILTERING_NODEBROADCAST 0x04

/*
-// RegAutoModes
-#define AUTOMODES_ENTER_OFF 0x00 // Default
-#define AUTOMODES_ENTER_FIFONOTEMPTY 0x20
-#define AUTOMODES_ENTER_FIFOLEVEL 0x40
-#define AUTOMODES_ENTER_CRCOK 0x60
-#define AUTOMODES_ENTER_PAYLOADREADY 0x80
-#define AUTOMODES_ENTER_SYNCADRSMATCH 0xA0
-#define AUTOMODES_ENTER_PACKETSENT 0xC0
-#define AUTOMODES_ENTER_FIFOEMPTY 0xE0
-
-#define AUTOMODES_EXIT_OFF 0x00 // Default
-#define AUTOMODES_EXIT_FIFOEMPTY 0x04
-#define AUTOMODES_EXIT_FIFOLEVEL 0x08
-#define AUTOMODES_EXIT_CRCOK 0x0C
-#define AUTOMODES_EXIT_PAYLOADREADY 0x10
-#define AUTOMODES_EXIT_SYNCADRSMATCH 0x14
-#define AUTOMODES_EXIT_PACKETSENT 0x18
-#define AUTOMODES_EXIT_RXTIMEOUT 0x1C
-
-#define AUTOMODES_INTERMEDIATE_SLEEP 0x00 // Default
-#define AUTOMODES_INTERMEDIATE_STANDBY 0x01
-#define AUTOMODES_INTERMEDIATE_RECEIVER 0x02
-#define AUTOMODES_INTERMEDIATE_TRANSMITTER 0x03
-
-*/
+ * // RegAutoModes
+ * #define AUTOMODES_ENTER_OFF 0x00 // Default
+ * #define AUTOMODES_ENTER_FIFONOTEMPTY 0x20
+ * #define AUTOMODES_ENTER_FIFOLEVEL 0x40
+ * #define AUTOMODES_ENTER_CRCOK 0x60
+ * #define AUTOMODES_ENTER_PAYLOADREADY 0x80
+ * #define AUTOMODES_ENTER_SYNCADRSMATCH 0xA0
+ * #define AUTOMODES_ENTER_PACKETSENT 0xC0
+ * #define AUTOMODES_ENTER_FIFOEMPTY 0xE0
+ *
+ * #define AUTOMODES_EXIT_OFF 0x00 // Default
+ * #define AUTOMODES_EXIT_FIFOEMPTY 0x04
+ * #define AUTOMODES_EXIT_FIFOLEVEL 0x08
+ * #define AUTOMODES_EXIT_CRCOK 0x0C
+ * #define AUTOMODES_EXIT_PAYLOADREADY 0x10
+ * #define AUTOMODES_EXIT_SYNCADRSMATCH 0x14
+ * #define AUTOMODES_EXIT_PACKETSENT 0x18
+ * #define AUTOMODES_EXIT_RXTIMEOUT 0x1C
+ *
+ * #define AUTOMODES_INTERMEDIATE_SLEEP 0x00 // Default
+ * #define AUTOMODES_INTERMEDIATE_STANDBY 0x01
+ * #define AUTOMODES_INTERMEDIATE_RECEIVER 0x02
+ * #define AUTOMODES_INTERMEDIATE_TRANSMITTER 0x03
+ *
+ */
/* RegFifoThresh (0x3c) */
#define MASK_FIFO_THRESH_TXSTART 0x80
#define MASK_FIFO_THRESH_VALUE 0x7F

/*
-
-// RegPacketConfig2
-#define PACKET2_RXRESTARTDELAY_1BIT 0x00 // Default
-#define PACKET2_RXRESTARTDELAY_2BITS 0x10
-#define PACKET2_RXRESTARTDELAY_4BITS 0x20
-#define PACKET2_RXRESTARTDELAY_8BITS 0x30
-#define PACKET2_RXRESTARTDELAY_16BITS 0x40
-#define PACKET2_RXRESTARTDELAY_32BITS 0x50
-#define PACKET2_RXRESTARTDELAY_64BITS 0x60
-#define PACKET2_RXRESTARTDELAY_128BITS 0x70
-#define PACKET2_RXRESTARTDELAY_256BITS 0x80
-#define PACKET2_RXRESTARTDELAY_512BITS 0x90
-#define PACKET2_RXRESTARTDELAY_1024BITS 0xA0
-#define PACKET2_RXRESTARTDELAY_2048BITS 0xB0
-#define PACKET2_RXRESTARTDELAY_NONE 0xC0
-#define PACKET2_RXRESTART 0x04
-
-#define PACKET2_AUTORXRESTART_ON 0x02 // Default
-#define PACKET2_AUTORXRESTART_OFF 0x00
-
-#define PACKET2_AES_ON 0x01
-#define PACKET2_AES_OFF 0x00 // Default
-
-
-// RegTemp1
-#define TEMP1_MEAS_START 0x08
-#define TEMP1_MEAS_RUNNING 0x04
-#define TEMP1_ADCLOWPOWER_ON 0x01 // Default
-#define TEMP1_ADCLOWPOWER_OFF 0x00
-*/
+ *
+ * // RegPacketConfig2
+ * #define PACKET2_RXRESTARTDELAY_1BIT 0x00 // Default
+ * #define PACKET2_RXRESTARTDELAY_2BITS 0x10
+ * #define PACKET2_RXRESTARTDELAY_4BITS 0x20
+ * #define PACKET2_RXRESTARTDELAY_8BITS 0x30
+ * #define PACKET2_RXRESTARTDELAY_16BITS 0x40
+ * #define PACKET2_RXRESTARTDELAY_32BITS 0x50
+ * #define PACKET2_RXRESTARTDELAY_64BITS 0x60
+ * #define PACKET2_RXRESTARTDELAY_128BITS 0x70
+ * #define PACKET2_RXRESTARTDELAY_256BITS 0x80
+ * #define PACKET2_RXRESTARTDELAY_512BITS 0x90
+ * #define PACKET2_RXRESTARTDELAY_1024BITS 0xA0
+ * #define PACKET2_RXRESTARTDELAY_2048BITS 0xB0
+ * #define PACKET2_RXRESTARTDELAY_NONE 0xC0
+ * #define PACKET2_RXRESTART 0x04
+ *
+ * #define PACKET2_AUTORXRESTART_ON 0x02 // Default
+ * #define PACKET2_AUTORXRESTART_OFF 0x00
+ *
+ * #define PACKET2_AES_ON 0x01
+ * #define PACKET2_AES_OFF 0x00 // Default
+ *
+ *
+ * // RegTemp1
+ * #define TEMP1_MEAS_START 0x08
+ * #define TEMP1_MEAS_RUNNING 0x04
+ * #define TEMP1_ADCLOWPOWER_ON 0x01 // Default
+ * #define TEMP1_ADCLOWPOWER_OFF 0x00
+ */

// RegTestDagc (0x6F)
#define DAGC_NORMAL 0x00 /* Reset value */
--
2.13.2

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