Re: [PATCH V1] one wire ds1wm patch

From: kbuild test robot
Date: Mon Jun 19 2017 - 13:39:01 EST


Hi Johannes,

[auto build test ERROR on linus/master]
[also build test ERROR on v4.12-rc6 next-20170619]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url: https://github.com/0day-ci/linux/commits/Johannes-P-hlmann/one-wire-ds1wm-patch/20170620-011329
config: x86_64-randconfig-x010-201725 (attached as .config)
compiler: gcc-6 (Debian 6.2.0-3) 6.2.0 20160901
reproduce:
# save the attached .config to linux build tree
make ARCH=x86_64

All errors (new ones prefixed by >>):

drivers/w1/masters/ds1wm.c: In function 'ds1wm_write_register':
>> drivers/w1/masters/ds1wm.c:126:4: error: implicit declaration of function 'writew_be' [-Werror=implicit-function-declaration]
writew_be((u16)val, ds1wm_data->map+(reg<<BUSWIDTH16));
^~~~~~~~~
>> drivers/w1/masters/ds1wm.c:129:4: error: implicit declaration of function 'writel_be' [-Werror=implicit-function-declaration]
writel_be((u32)val, ds1wm_data->map+(reg<<BUSWIDTH32));
^~~~~~~~~
drivers/w1/masters/ds1wm.c: In function 'ds1wm_read_register':
>> drivers/w1/masters/ds1wm.c:165:10: error: implicit declaration of function 'readw_be' [-Werror=implicit-function-declaration]
val = readw_be(ds1wm_data->map + (reg << BUSWIDTH16));
^~~~~~~~
>> drivers/w1/masters/ds1wm.c:168:10: error: implicit declaration of function 'readl_be' [-Werror=implicit-function-declaration]
val = readl_be(ds1wm_data->map + (reg << BUSWIDTH32));
^~~~~~~~
cc1: some warnings being treated as errors

vim +/writew_be +126 drivers/w1/masters/ds1wm.c

120 if (ds1wm_data->isHwBigEndian) {
121 switch (ds1wm_data->bus_shift) {
122 case BUSWIDTH8:
123 writeb(val, ds1wm_data->map + (reg << BUSWIDTH8));
124 break;
125 case BUSWIDTH16:
> 126 writew_be((u16)val, ds1wm_data->map+(reg<<BUSWIDTH16));
127 break;
128 case BUSWIDTH32:
> 129 writel_be((u32)val, ds1wm_data->map+(reg<<BUSWIDTH32));
130 break;
131 default:
132 dev_err(&ds1wm_data->pdev->dev,
133 "illegal bus shift %d, not written",
134 ds1wm_data->bus_shift);
135 }
136 } else {
137 switch (ds1wm_data->bus_shift) {
138 case BUSWIDTH8:
139 writeb(val, ds1wm_data->map + (reg << BUSWIDTH8));
140 break;
141 case BUSWIDTH16:
142 writew((u16) val, ds1wm_data->map+(reg << BUSWIDTH16));
143 break;
144 case BUSWIDTH32:
145 writel((u32) val, ds1wm_data->map+(reg << BUSWIDTH32));
146 break;
147 default:
148 dev_err(&ds1wm_data->pdev->dev,
149 "illegal bus shift %d, not written",
150 ds1wm_data->bus_shift);
151 }
152 }
153 }
154
155 static inline u8 ds1wm_read_register(struct ds1wm_data *ds1wm_data, u32 reg)
156 {
157
158 u32 val = 0;
159 if (ds1wm_data->isHwBigEndian) {
160 switch (ds1wm_data->bus_shift) {
161 case BUSWIDTH8:
162 val = readb(ds1wm_data->map + (reg << BUSWIDTH8));
163 break;
164 case BUSWIDTH16:
> 165 val = readw_be(ds1wm_data->map + (reg << BUSWIDTH16));
166 break;
167 case BUSWIDTH32:
> 168 val = readl_be(ds1wm_data->map + (reg << BUSWIDTH32));
169 break;
170 default:
171 dev_err(&ds1wm_data->pdev->dev,

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