Re: [PATCH v2] tile: handle __ro_after_init like parisc does

From: Kees Cook
Date: Mon Nov 14 2016 - 16:12:12 EST


On Mon, Nov 14, 2016 at 12:29 PM, Chris Metcalf <cmetcalf@xxxxxxxxxxxx> wrote:
> The tile architecture already marks RO_DATA as read-only in
> the kernel, so grouping RO_AFTER_INIT_DATA with RO_DATA, as is
> done by default, means the kernel faults in init when it tries
> to write to RO_AFTER_INIT_DATA. For now, just arrange that
> __ro_after_init is handled like __write_once, i.e. __read_mostly.
>
> Signed-off-by: Chris Metcalf <cmetcalf@xxxxxxxxxxxx>

Reviewed-by: Kees Cook <keescook@xxxxxxxxxxxx>

At some point here, I want to collect all the arch maintainers and
discuss the options for correctly reflecting the three data
memory-protection needs we have:

- always read-only
- read-only after init
- read-only except during rare updates

(The latter one doesn't exist all yet...)

x86, arm, and arm64 use mark_rodata_ro() after init finishes, so they
don't technically implement "always read-only". parisc, tile, powerpc,
others have "always read-only", but disable read-only-after-init since
they don't use mark_rodata_ro(). I think s390 has recently implemented
both, but I have to double-check...

-Kees

> ---
> arch/tile/include/asm/cache.h | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/arch/tile/include/asm/cache.h b/arch/tile/include/asm/cache.h
> index 6160761d5f61..4810e48dbbbf 100644
> --- a/arch/tile/include/asm/cache.h
> +++ b/arch/tile/include/asm/cache.h
> @@ -61,4 +61,7 @@
> */
> #define __write_once __read_mostly
>
> +/* __ro_after_init is the generic name for the tile arch __write_once. */
> +#define __ro_after_init __read_mostly
> +
> #endif /* _ASM_TILE_CACHE_H */
> --
> 2.7.2
>



--
Kees Cook
Nexus Security