Re: [REF PATCH] x86/tlb: just do tlb flush on one of siblings of SMT

[Andy Lutomirski]

On Apr 5, 2016 8:17 PM, "Alex Shi" <alex.shi@xxxxxxxxxx> wrote:
>
> It seems Intel core still share the TLB pool, flush both of threads' TLB
> just cause a extra useless IPI and a extra flush. The extra flush will
> flush out TLB again which another thread just introduced.
> That's double waste.

Do you have a reference in both the SDM and the APM for this?

Do we have a guarantee that this serialized the front end such that
the non-targetted sibling won't execute an instruction that it decoded
from a stale translation?

This will conflict rather deeply with my PCID series, too.

--Andy