Re: [PATCH v4 5/7] Watchdog: introduce ARM SBSA watchdog driver

[Guenter Roeck]

On 06/09/2015 03:46 AM, Fu Wei wrote:

> Yes, if WOR only affect in TimeoutRefresh, we cat always make WOR == pretimeout
> But the problem is  if we enable watchdog (write 0x01 to WCS will
> cause an explicit watchdog refresh), then
> 1) if ExplicitRefresh = True:
>           CompareValue := SystemCounter + WOR
>           WS0 := True
> 2) TimeoutRefresh is True again, WS0 == True:
>           WS1 = True
>
> so once we enable watchdog, system reset, that is not what we want.
> this behavior is following SBSA spec.

Ok, I admit I am a bit slow ;-).

WS0 := True would be set the next time around, since

	if ExplicitRefresh == True
		WS0 = False
		WS1 = False

but I see your point. Essentially, the specification is broken
for all practical purposes, since, as you point out, enabling
the watchdog overwrites and explicitly sets WCV. Effectively
this means that just using WCV to program the timeout period
is not really possible.

I am not really sure how to address this. We can either only use WOR,
and forget about pretimeout, or we can enforce a minimum pretimeout.
In the latter case, we'll have to write WCV after writing WOR.

Thanks,
Guenter

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