Re: [PATCH 02/10] perf/x86: Improve HT workaround GP counter constraint

[Ingo Molnar]

* Peter Zijlstra <peterz@xxxxxxxxxxxxx> wrote:

> On Fri, May 22, 2015 at 06:40:49AM -0700, Stephane Eranian wrote:
> > On Fri, May 22, 2015 at 6:36 AM, Peter Zijlstra <peterz@xxxxxxxxxxxxx> wrote:
> > > On Fri, May 22, 2015 at 06:29:47AM -0700, Stephane Eranian wrote:
> > >> On Fri, May 22, 2015 at 6:25 AM, Peter Zijlstra <peterz@xxxxxxxxxxxxx> wrote:
> > >> > On Fri, May 22, 2015 at 06:07:00AM -0700, Stephane Eranian wrote:
> > >> >>
> > >> >> One other thing I noticed is that the --n_excl needs to be protected by the
> > >> >> excl_cntrs->lock in put_excl_constraints().
> > >> >
> > >> > Nah, its strictly per cpu.
> > >>
> > >> No. the excl_cntrs struct is pointed to by cpuc but it is shared between the
> > >> sibling HT. Otherwise this would not work!
> > >
> > > n_excl is per cpuc, see the trickery with has_exclusive vs
> > > exclusive_present on how I avoid the lock.
> > 
> > Yes, but I believe  you create a store forward penalty with this.
> > You store 16bits and you load 32 bits on the same cache line.

Same cacheline access has no such penalty: only if the partial access 
is for the same word.

> The store and load are fairly well spaced -- the entire scheduling 
> fast path is in between.
> 
> And such a penalty is still cheap compared to locking, no?

The 'penalty' is essentially just a delay in the execution of the 
load, if the store has not finished yet: typically less than 10 
cycles, around 3 cycles on recent uarchs.

So it should not be a big issue if there's indeed so much code between 
them - probably it's not even causing any delay anywhere.

Thanks,

	Ingo
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