Re: [PATCH 1/1] clk: tegra: read correct iddq register in PLL_SS registration

From: Benson Leung
Date: Mon May 18 2015 - 12:53:22 EST


On Mon, May 18, 2015 at 4:03 AM, Bill Huang <bilhuang@xxxxxxxxxx> wrote:
> This fixes bug in tegra_clk_register_pllss() which mistakenly assume the
> iddq register is the PLL base address.
>
> Signed-off-by: Bill Huang <bilhuang@xxxxxxxxxx>

Thanks for the quick fix.
Reviewed-by: Benson Leung <bleung@xxxxxxxxxxxx>

--
Benson Leung
Software Engineer, Chrom* OS
bleung@xxxxxxxxxxxx
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