Re: [PATCH 1/2] i2c: tegra: Maintain CPU endianness

From: Wolfram Sang
Date: Mon Jan 26 2015 - 11:03:52 EST

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> Gaahh! I'm sure it wasn't working before! I'll make more testing and send v3
> without "val = 0", if all will be fine.

Please either send V3 or explicitly say V2 is OK. No need to hurry, just
saying that I am waiting for updates here...

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Next message: Nicolas Ferre: "Re: [PATCH v2 02/12] pm: at91: Workaround DDRSDRC self-refresh bug with LPDDR1 memories."
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