Yes, the 3 memory areas are part of the packet sniffer module.
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+* Linn Products Ethernet Packet Sniffer
+
+Required properties:
+- compatible : must be "linn,eth-sniffer"
+- reg : physical addresses and sizes of registers. Must contain 3 entries:
+ first entry: registers memory space
+ second entry: TX command memory
+ third entry: RX command memory
Just to check: are those memories are part of the packet sniffer device,
or are carveouts from other memory?
The packet sniffer sits between the MAC and the PHY and monitors TX or RX+- fifo-block-words : number of words in one data FIFO entrySurely the relationship between the sniffer, MAC, and PHY should be
+
+Example:
+
+sniffer@1814a000 {
+ compatible = "linn,eth-sniffer";
+ reg = <0x1814a000 0x100>, <0x1814a400 0x400>, <0x1814a800 0x400>;
+ reg-names = "regs", "tx-ram", "rx-ram";
+ interrupts = <GIC_SHARED 58 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eth-sniffer-irq";
+ clocks = <&system_clk>;
+ clock-names = "sys";
+ fifo-block-words = <4>;
+ };
described, so we know which interface the sniffer is related to?