Re: [PATCH v5 4/7] ARM: l2c: Add support for overriding prefetch settings

[Mark Rutland]

On Wed, Sep 24, 2014 at 12:05:38PM +0100, Marek Szyprowski wrote:
> From: Tomasz Figa <t.figa@xxxxxxxxxxx>
> 
> Firmware on certain boards (e.g. ODROID-U3) can leave incorrect L2C prefetch
> settings configured in registers leading to crashes if L2C is enabled
> without overriding them. This patch introduces bindings to enable
> prefetch settings to be specified from DT and necessary support in the
> driver.
> 
> Signed-off-by: Tomasz Figa <t.figa@xxxxxxxxxxx>
> Signed-off-by: Marek Szyprowski <m.szyprowski@xxxxxxxxxxx>
> ---
>  Documentation/devicetree/bindings/arm/l2cc.txt | 10 +++++++
>  arch/arm/mm/cache-l2x0.c                       | 39 ++++++++++++++++++++++++++
>  2 files changed, 49 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/arm/l2cc.txt b/Documentation/devicetree/bindings/arm/l2cc.txt
> index af527ee111c2..3443d2d76788 100644
> --- a/Documentation/devicetree/bindings/arm/l2cc.txt
> +++ b/Documentation/devicetree/bindings/arm/l2cc.txt
> @@ -47,6 +47,16 @@ Optional properties:
>  - cache-id-part: cache id part number to be used if it is not present
>    on hardware
>  - wt-override: If present then L2 is forced to Write through mode
> +- arm,double-linefill : Override double linefill enable setting. Enable if
> +  non-zero, disable if zero.
> +- arm,double-linefill-incr : Override double linefill on INCR read. Enable
> +  if non-zero, disable if zero.
> +- arm,double-linefill-wrap : Override double linefill on WRAP read. Enable
> +  if non-zero, disable if zero.
> +- arm,prefetch-drop : Override prefetch drop enable setting. Enable if non-zero,
> +  disable if zero.

I'm not too keen on tristate properties. Is this level of flexibility
really required?

What exact overrides do you need for boards you know of? Why do these
cause crashes if not overridden?

Mark.

> +- arm,prefetch-offset : Override prefetch offset value. Valid values are
> +  0-7, 15, 23, and 31.
>  
>  Example:
>  
> diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
> index 84c6c55ab896..af90a6ff6b49 100644
> --- a/arch/arm/mm/cache-l2x0.c
> +++ b/arch/arm/mm/cache-l2x0.c
> @@ -1059,6 +1059,8 @@ static void __init l2c310_of_parse(const struct device_node *np,
>  	u32 data[3] = { 0, 0, 0 };
>  	u32 tag[3] = { 0, 0, 0 };
>  	u32 filter[2] = { 0, 0 };
> +	u32 prefetch;
> +	u32 val;
>  
>  	of_property_read_u32_array(np, "arm,tag-latency", tag, ARRAY_SIZE(tag));
>  	if (tag[0] && tag[1] && tag[2])
> @@ -1083,6 +1085,43 @@ static void __init l2c310_of_parse(const struct device_node *np,
>  		l2x0_saved_regs.filter_start = (filter[0] & ~(SZ_1M - 1))
>  					| L310_ADDR_FILTER_EN;
>  	}
> +
> +	prefetch = l2x0_saved_regs.prefetch_ctrl;
> +
> +	if (!of_property_read_u32(np, "arm,double-linefill", &val)) {
> +		if (val)
> +			prefetch |= L310_PREFETCH_CTRL_DBL_LINEFILL;
> +		else
> +			prefetch &= ~L310_PREFETCH_CTRL_DBL_LINEFILL;
> +	}
> +
> +	if (!of_property_read_u32(np, "arm,double-linefill-incr", &val)) {
> +		if (val)
> +			prefetch |= L310_PREFETCH_CTRL_DBL_LINEFILL_INCR;
> +		else
> +			prefetch &= ~L310_PREFETCH_CTRL_DBL_LINEFILL_INCR;
> +	}
> +
> +	if (!of_property_read_u32(np, "arm,double-linefill-wrap", &val)) {
> +		if (!val)
> +			prefetch |= L310_PREFETCH_CTRL_DBL_LINEFILL_WRAP;
> +		else
> +			prefetch &= ~L310_PREFETCH_CTRL_DBL_LINEFILL_WRAP;
> +	}
> +
> +	if (!of_property_read_u32(np, "arm,prefetch-drop", &val)) {
> +		if (val)
> +			prefetch |= L310_PREFETCH_CTRL_PREFETCH_DROP;
> +		else
> +			prefetch &= ~L310_PREFETCH_CTRL_PREFETCH_DROP;
> +	}
> +
> +	if (!of_property_read_u32(np, "arm,prefetch-offset", &val)) {
> +		prefetch &= ~L310_PREFETCH_CTRL_OFFSET_MASK;
> +		prefetch |= val & L310_PREFETCH_CTRL_OFFSET_MASK;
> +	}
> +
> +	l2x0_saved_regs.prefetch_ctrl = prefetch;
>  }
>  
>  static const struct l2c_init_data of_l2c310_data __initconst = {
> -- 
> 1.9.2
> 
> 
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