[PATCH 3.12 053/146] clk: tegra: Fix wrong value written to PLLE_AUX

[Jiri Slaby]

From: Tuomas Tynkkynen <ttynkkynen@xxxxxxxxxx>

3.12-stable review patch.  If anyone has any objections, please let me know.

===============

commit d2c834abe2b39a2d5a6c38ef44de87c97cbb34b4 upstream.

The value written to PLLE_AUX was incorrect due to a wrong variable
being used. Without this fix SATA does not work.

Signed-off-by: Tuomas Tynkkynen <ttynkkynen@xxxxxxxxxx>
Tested-by: Mikko Perttunen <mperttunen@xxxxxxxxxx>
Reviewed-by: Thierry Reding <treding@xxxxxxxxxx>
Tested-by: Thierry Reding <treding@xxxxxxxxxx>
Acked-by: Thierry Reding <treding@xxxxxxxxxx>
Signed-off-by: Mike Turquette <mturquette@xxxxxxxxxx>
[mturquette@xxxxxxxxxx: improved changelog]
Signed-off-by: Jiri Slaby <jslaby@xxxxxxx>
---
 drivers/clk/tegra/clk-pll.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index e09f09ce44f8..4c1d9bbe3191 100644
--- a/drivers/clk/tegra/clk-pll.c
+++ b/drivers/clk/tegra/clk-pll.c
@@ -1594,7 +1594,7 @@ struct clk *tegra_clk_register_plle_tegra114(const char *name,
 					"pll_re_vco");
 	} else {
 		val_aux &= ~(PLLE_AUX_PLLRE_SEL | PLLE_AUX_PLLP_SEL);
-		pll_writel(val, pll_params->aux_reg, pll);
+		pll_writel(val_aux, pll_params->aux_reg, pll);
 	}
 
 	clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
-- 
1.9.3

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