Re: [PATCH 2/3] perf, ARM: use common PMU interrupt disabled code

[Will Deacon]

On Fri, May 16, 2014 at 10:15:49PM +0100, Vince Weaver wrote:
> 
> Make the ARM perf code use the new common PMU interrupt disabled code.
> 
> This allows perf to work on ARM machines without a working PMU
> interrupt (for example, raspberry pi).
> 
> Signed-off-by: Vince Weaver <vincent.weaver@xxxxxxxxx>
> 
> diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c
> index a6bc431..4238bcb 100644
> --- a/arch/arm/kernel/perf_event.c
> +++ b/arch/arm/kernel/perf_event.c
> @@ -410,7 +410,7 @@ __hw_perf_event_init(struct perf_event *event)
>  	 */
>  	hwc->config_base	    |= (unsigned long)mapping;
>  
> -	if (!hwc->sample_period) {
> +	if (!is_sampling_event(event)) {
>  		/*
>  		 * For non-sampling runs, limit the sample_period to half
>  		 * of the counter width. That way, the new counter value
> diff --git a/arch/arm/kernel/perf_event_cpu.c b/arch/arm/kernel/perf_event_cpu.c
> index 51798d7..63d95fa 100644
> --- a/arch/arm/kernel/perf_event_cpu.c
> +++ b/arch/arm/kernel/perf_event_cpu.c
> @@ -126,8 +126,8 @@ static int cpu_pmu_request_irq(struct arm_pmu *cpu_pmu, irq_handler_t handler)
>  
>  	irqs = min(pmu_device->num_resources, num_possible_cpus());
>  	if (irqs < 1) {
> -		pr_err("no irqs for PMUs defined\n");
> -		return -ENODEV;
> +		printk_once("no irqs for PMU defined, sampled events not supported\n");

s/sampled/sampling/

> +		return 0;
>  	}
>  
>  	irq = platform_get_irq(pmu_device, 0);
> @@ -191,6 +191,11 @@ static void cpu_pmu_init(struct arm_pmu *cpu_pmu)
>  	/* Ensure the PMU has sane values out of reset. */
>  	if (cpu_pmu->reset)
>  		on_each_cpu(cpu_pmu->reset, cpu_pmu, 1);
> +
> +	/* If no interrupts available, set the corresponding capability flag */
> +	if (platform_get_irq(cpu_pmu->plat_device, 0) <= 0) {

I think you can just do if (!platform_get_irq(cpu_pmu->plat_device, 0))
here (I appreciate the ARM perf code isn't consistent here).

Anyway, with those minor changes:

  Acked-by: Will Deacon <will.deacon@xxxxxxx>

Thanks,

Will
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