Re: [PATCH v2]: fix Haswell precise store data source encoding

[Don Zickus]

On Thu, May 15, 2014 at 10:08:51PM +0200, Stephane Eranian wrote:
> On Thu, May 15, 2014 at 9:56 PM, Don Zickus <dzickus@xxxxxxxxxx> wrote:
> > On Thu, May 15, 2014 at 05:56:44PM +0200, Stephane Eranian wrote:
> >>
> >> This patch fixes a bug in  precise_store_data_hsw() whereby
> >> it would set the data source memory level to the wrong value.
> >>
> >> As per the the SDM Vol 3b Table 18-41 (Layout of Data Linear
> >> Address Information in PEBS Record), when status bit 0 is set
> >> this is a L1 hit, otherwise this is a L1 miss.
> >>
> >> This patch encodes the memory level according to the specification.
> >>
> >> In V2, we added the filtering on the store events.
> >> Only the following events produce L1 information:
> >>  * MEM_UOPS_RETIRED.STLB_MISS_STORES
> >>  * MEM_UOPS_RETIRED.LOCK_STORES
> >>  * MEM_UOPS_RETIRED.SPLIT_STORES
> >>  * MEM_UOPS_RETIRED.ALL_STORES
> >
> > This worked great on our Haswell-EX box.  I was a little surprised to find
> > out it did until I realized on Ivy Bridge 'mem-store' was a 0x02cd but on
> > Haswell it is now a 0x82d0.  Go generic event types! :-)
> >
> > Looking at the SDM documentation it does say something about
> > 'UOPS_RETIRED.ALL' supporting stores too but can't find that event.  Is
> > that a typo, much like the 0x02 umask for stores on the D0 event is
> > missing from the documentation?  Just wanted to make sure we are not
> > missing one more case.
> >
> But uops_retired.all does not generate the L1 info. That is why it is not
> there in my patch.

Ok.

Cheers,
Don
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