Re: [PATCH v1 06/11] mmc: mmci: Qcomm: Add 3 clock cycle delay after register write

[Srinivas Kandagatla]

Thanks Linus W for reviewing the patches.

On 13/05/14 08:29, Linus Walleij wrote:
> On Tue, Apr 29, 2014 at 10:20 AM,  <srinivas.kandagatla@xxxxxxxxxx> wrote:
>
> > From: Srinivas Kandagatla <srinivas.kandagatla@xxxxxxxxxx>
> >
> > Most of the Qcomm SD card controller registers must be updated to the MCLK
> > domain so subsequent writes to registers will be ignored until 3 clock cycles
> > have passed.
> >
> > This patch adds a 3 clock cycle delay required after writing to controller
> > registers on Qualcomm SOCs. Without this delay all the register writes are not
> > successfull, resulting in not detecting cards.
> >
> > Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@xxxxxxxxxx>
>
> Sounds like someone decided to clock the internal state machine
> in the MMCI using MCLK instead of PCLK :-(
>
> A bit nasty if this ends up in the fastpath (irq) though. Which it
> invariably does, right?
yes, Its going to for Qcom SOC.
> > +       /*
> > +        * On QCom SD card controller, registers must be updated to the
> > +        * MCLK domain so subsequent writes to this register will be ignored
> > +        * for 3 clk cycles.
> > +        */
> > +       if (host->hw_designer == AMBA_VENDOR_QCOM)
> > +               udelay(1 + ((3 * USEC_PER_SEC)/host->mclk));
>
> Add a new field in vendor data instead, and use DIV_ROUND_UP():
yes, that makes sense..

> static struct variant_data variant_qcom = {
>           .mclk_delayed_writes  = true,
> (...)
>
> if (host->vendor->mclk_delayed_writes)
>      udelay(DIV_ROUND_UP((3 * USEC_PER_SEC), host->mclk));
>
> You get the idea.
Got it.

> Yours,
> Linus Walleij
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