Oleksandr Dmytryshyn <oleksandr.dmytryshyn@xxxxxx> writes:Hi, Kevin.
On 05/29/2013 08:22 PM, Kevin Hilman wrote:Yes, I understand why your patch works, and it looks correct to me.Oleksandr Dmytryshyn <oleksandr.dmytryshyn@xxxxxx> writes:Hi, Kevin.
Starting from the OMAP chips with version2 registers scheme there areWhy? (changelogs should always answer the "why" question)
2 registers (I2C_IRQENABLE_SET and I2C_IRQENABLE_CLR) to manage
interrupts instead of the older OMAP chips with old scheme which have
only one register (I2C_IE). Now we should use I2C_IRQENABLE_SET
register for enabling interrupts and I2C_IRQENABLE_CLR register for
disabling interrupts.
IOW, what is broken without this change, how does it fail? And equally
important, how is it currently working?
Kevin
If the i2c controller during suspend will generate an interrupt, it
can lead to unpredictable behaviour in the kernel.
Based on the logic of the kernel code interrupts from i2c should be
prohibited during suspend. Kernel writes 0 to the I2C_IE register in
the omap_i2c_runtime_suspend() function. In the other side kernel
writes saved interrupt flags to the I2C_IE register in
omap_i2c_runtime_resume() function. I.e. interrupts should be disabled
during suspend.
This works for chips with version1 registers scheme. Interrupts are
disabled during suspend. For chips with version2 scheme registers
writting 0 to the I2C_IE register does nothing (because now the
I2C_IRQENABLE_SET register is located at this address ). This register
is used to enable interrupts. For disabling interrupts
I2C_IRQENABLE_CLR register should be used.
I've checked that interrupts in the i2c controller are still enabled
after writting 0 to the I2C_IE register. But with my patch interrupts
are disabled in the omap_i2c_runtime_suspend() function.
My main concern is that the changelog is missing a detailed description
of the problem that is being solved, as well as a summary of why this
has ever worked. I guess we've just been lucky and not seen interrupts
during suspend?
Kevin