MTD NAND BCH support for 24 bits/1K of ECC correction?

[Aaron Williams]

Hi all,

I am trying to clean up our OCTEON NAND flash driver in the Linux kernel 
and enable support for multi-bit ECC using BCH and am having some 
issues. I am able to successfully work with NAND flash that requires 4 
bits ECC per 512 bytes but I am having issues with one of our boards 
that has a NAND device that requires 24 bits of ECC per 1024 bytes.

I was wondering if ECC of this magnitude has been successfully tested in 
the past. By my calculations I should have 42 bytes of ECC per 1K block 
(m=14, t=24 for 336 bits of ECC data). My problem is that when decoding 
an encoded block I am seeing that nroots != err in decode_bch() after 
find_poly_roots(). I am seeing this for all of the blocks I attempt to 
read. As far as I can tell the data being sent to BCH is good, though it 
might have a few bad bits but nowhere near 24.

I am also seeing this same behavior in my U-Boot code which uses the 
identical bch and nand_bch code.

Cheers,

Aaron Williams

--
Aaron Williams
Software Engineer
Cavium, Inc.
(408) 943-7198  (510) 789-8988 (cell)


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