Re: [PATCH 22/31] perf, core: Define generic hardware transactionevents

[Peter Zijlstra]

On Thu, 2012-09-27 at 21:31 -0700, Andi Kleen wrote:
> From: Andi Kleen <ak@xxxxxxxxxxxxxxx>
> 
> For tuning and debugging hardware transactional memory it is very
> important to have hardware counter support.
> 
> This patch adds a simple and hopefully generic set of hardware events
> for transactional memory and lock elision.
> 
> It is based on the TSX PMU support because I don't have any
> information on other CPU's HTM support.
> 
> There are start, commit and abort events for transactions and
> for lock elision.
> 
> The abort events are qualified by a generic abort reason that should
> be roughly applicable to a wide range of memory transaction systems:
> 
> capacity for the buffering capacity
> conflict for a dynamic conflict between CPUs
> all      for all aborts. On TSX this can be precisely sampled.
> 
> We need to split the events into general transaction events and lock
> elision events. Architecturs with HTM but no lock elision would only
> use the first set.
> 
> Implementation for Haswell in a followon patch.

I would much prefer sysfs events over yet another weird event class
here. That also solves the problem of not knowing wtf other cpus might
or might not do.
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