Re: [PATCH V6 08/13] perf: Add Sandy Bridge-EP uncore support

[Stephane Eranian]

On Fri, Jun 15, 2012 at 8:31 AM, Yan, Zheng <zheng.z.yan@xxxxxxxxx> wrote:
> From: "Yan, Zheng" <zheng.z.yan@xxxxxxxxx>
>
> Add Intel Nehalem and Sandy Bridge uncore pmu support. The uncore
> subsystem in Sandy Bridge-EP consists of 8 components (Ubox,
> Cacheing Agent, Home Agent, Memory controller, Power Control,
> QPI Link Layer, R2PCIe, R3QPI).
>
I did not find in this patch the support for the C-Box Filter register
(SNBEP_C0_MSR_PMON_BOX_FILTER). Based on the description
in the manual, looks like a valuable filter to support, especially for
the core/thread filtering capability.

There is only one such filter per box, and it can be used by any events.
So looks like we have another offcore_resp style register to manage
here. Need to ensure the value of that filter is shared by all 4 counters.
If you were to support that, you'd have to enable the tid filter on the
CBox config regs and export that via sysfs. Also I assume you'd
pass the value of that filter either in config1 or in the upper 32 bits
of the config reg.

What's your take on that?




> Signed-off-by: Zheng Yan <zheng.z.yan@xxxxxxxxx>
> ---
> Âarch/x86/kernel/cpu/perf_event_intel_uncore.c | Â484 +++++++++++++++++++++++++
> Âarch/x86/kernel/cpu/perf_event_intel_uncore.h | Â 86 +++++
> Âinclude/linux/pci_ids.h            |  11 +
> Â3 files changed, 581 insertions(+), 0 deletions(-)
>
> diff --git a/arch/x86/kernel/cpu/perf_event_intel_uncore.c b/arch/x86/kernel/cpu/perf_event_intel_uncore.c
> index 2449d8d..0bc6148 100644
> --- a/arch/x86/kernel/cpu/perf_event_intel_uncore.c
> +++ b/arch/x86/kernel/cpu/perf_event_intel_uncore.c
> @@ -21,6 +21,482 @@ DEFINE_UNCORE_FORMAT_ATTR(edge, edge, "config:18");
> ÂDEFINE_UNCORE_FORMAT_ATTR(inv, inv, "config:23");
> ÂDEFINE_UNCORE_FORMAT_ATTR(cmask5, cmask, "config:24-28");
> ÂDEFINE_UNCORE_FORMAT_ATTR(cmask8, cmask, "config:24-31");
> +DEFINE_UNCORE_FORMAT_ATTR(thresh8, thresh, "config:24-31");
> +DEFINE_UNCORE_FORMAT_ATTR(thresh5, thresh, "config:24-28");
> +DEFINE_UNCORE_FORMAT_ATTR(occ_sel, occ_sel, "config:14-15");
> +DEFINE_UNCORE_FORMAT_ATTR(occ_invert, occ_invert, "config:30");
> +DEFINE_UNCORE_FORMAT_ATTR(occ_edge, occ_edge, "config:14-51");
> +
> +/* Sandy Bridge-EP uncore support */
> +static void snbep_uncore_pci_disable_box(struct intel_uncore_box *box)
> +{
> + Â Â Â struct pci_dev *pdev = box->pci_dev;
> + Â Â Â int box_ctl = uncore_pci_box_ctl(box);
> + Â Â Â u32 config;
> +
> + Â Â Â pci_read_config_dword(pdev, box_ctl, &config);
> + Â Â Â config |= SNBEP_PMON_BOX_CTL_FRZ;
> + Â Â Â pci_write_config_dword(pdev, box_ctl, config);
> +}
> +
> +static void snbep_uncore_pci_enable_box(struct intel_uncore_box *box)
> +{
> + Â Â Â struct pci_dev *pdev = box->pci_dev;
> + Â Â Â int box_ctl = uncore_pci_box_ctl(box);
> + Â Â Â u32 config;
> +
> + Â Â Â pci_read_config_dword(pdev, box_ctl, &config);
> + Â Â Â config &= ~SNBEP_PMON_BOX_CTL_FRZ;
> + Â Â Â pci_write_config_dword(pdev, box_ctl, config);
> +}
> +
> +static void snbep_uncore_pci_enable_event(struct intel_uncore_box *box,
> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â struct perf_event *event)
> +{
> + Â Â Â struct pci_dev *pdev = box->pci_dev;
> + Â Â Â struct hw_perf_event *hwc = &event->hw;
> +
> + Â Â Â pci_write_config_dword(pdev, hwc->config_base, hwc->config |
> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â SNBEP_PMON_CTL_EN);
> +}
> +
> +static void snbep_uncore_pci_disable_event(struct intel_uncore_box *box,
> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â struct perf_event *event)
> +{
> + Â Â Â struct pci_dev *pdev = box->pci_dev;
> + Â Â Â struct hw_perf_event *hwc = &event->hw;
> +
> + Â Â Â pci_write_config_dword(pdev, hwc->config_base, hwc->config);
> +}
> +
> +static u64 snbep_uncore_pci_read_counter(struct intel_uncore_box *box,
> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â struct perf_event *event)
> +{
> + Â Â Â struct pci_dev *pdev = box->pci_dev;
> + Â Â Â struct hw_perf_event *hwc = &event->hw;
> + Â Â Â u64 count;
> +
> + Â Â Â pci_read_config_dword(pdev, hwc->event_base, (u32 *)&count);
> + Â Â Â pci_read_config_dword(pdev, hwc->event_base + 4, (u32 *)&count + 1);
> + Â Â Â return count;
> +}
> +
> +static void snbep_uncore_pci_init_box(struct intel_uncore_box *box)
> +{
> + Â Â Â struct pci_dev *pdev = box->pci_dev;
> + Â Â Â pci_write_config_dword(pdev, SNBEP_PCI_PMON_BOX_CTL,
> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â SNBEP_PMON_BOX_CTL_INT);
> +}
> +
> +static void snbep_uncore_msr_disable_box(struct intel_uncore_box *box)
> +{
> + Â Â Â u64 config;
> + Â Â Â unsigned msr;
> +
> + Â Â Â msr = uncore_msr_box_ctl(box);
> + Â Â Â if (msr) {
> + Â Â Â Â Â Â Â rdmsrl(msr, config);
> + Â Â Â Â Â Â Â config |= SNBEP_PMON_BOX_CTL_FRZ;
> + Â Â Â Â Â Â Â wrmsrl(msr, config);
> + Â Â Â Â Â Â Â return;
> + Â Â Â }
> +}
> +
> +static void snbep_uncore_msr_enable_box(struct intel_uncore_box *box)
> +{
> + Â Â Â u64 config;
> + Â Â Â unsigned msr;
> +
> + Â Â Â msr = uncore_msr_box_ctl(box);
> + Â Â Â if (msr) {
> + Â Â Â Â Â Â Â rdmsrl(msr, config);
> + Â Â Â Â Â Â Â config &= ~SNBEP_PMON_BOX_CTL_FRZ;
> + Â Â Â Â Â Â Â wrmsrl(msr, config);
> + Â Â Â Â Â Â Â return;
> + Â Â Â }
> +}
> +
> +static void snbep_uncore_msr_enable_event(struct intel_uncore_box *box,
> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â struct perf_event *event)
> +{
> + Â Â Â struct hw_perf_event *hwc = &event->hw;
> +
> + Â Â Â wrmsrl(hwc->config_base, hwc->config | SNBEP_PMON_CTL_EN);
> +}
> +
> +static void snbep_uncore_msr_disable_event(struct intel_uncore_box *box,
> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â struct perf_event *event)
> +{
> + Â Â Â struct hw_perf_event *hwc = &event->hw;
> +
> + Â Â Â wrmsrl(hwc->config_base, hwc->config);
> +}
> +
> +static u64 snbep_uncore_msr_read_counter(struct intel_uncore_box *box,
> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â struct perf_event *event)
> +{
> + Â Â Â struct hw_perf_event *hwc = &event->hw;
> + Â Â Â u64 count;
> +
> + Â Â Â rdmsrl(hwc->event_base, count);
> + Â Â Â return count;
> +}
> +
> +static void snbep_uncore_msr_init_box(struct intel_uncore_box *box)
> +{
> + Â Â Â unsigned msr = uncore_msr_box_ctl(box);
> + Â Â Â if (msr)
> + Â Â Â Â Â Â Â wrmsrl(msr, SNBEP_PMON_BOX_CTL_INT);
> +}
> +
> +static struct attribute *snbep_uncore_formats_attr[] = {
> + Â Â Â &format_attr_event.attr,
> + Â Â Â &format_attr_umask.attr,
> + Â Â Â &format_attr_edge.attr,
> + Â Â Â &format_attr_inv.attr,
> + Â Â Â &format_attr_thresh8.attr,
> + Â Â Â NULL,
> +};
> +
> +static struct attribute *snbep_uncore_ubox_formats_attr[] = {
> + Â Â Â &format_attr_event.attr,
> + Â Â Â &format_attr_umask.attr,
> + Â Â Â &format_attr_edge.attr,
> + Â Â Â &format_attr_inv.attr,
> + Â Â Â &format_attr_thresh5.attr,
> + Â Â Â NULL,
> +};
> +
> +static struct attribute *snbep_uncore_pcu_formats_attr[] = {
> + Â Â Â &format_attr_event.attr,
> + Â Â Â &format_attr_occ_sel.attr,
> + Â Â Â &format_attr_edge.attr,
> + Â Â Â &format_attr_inv.attr,
> + Â Â Â &format_attr_thresh5.attr,
> + Â Â Â &format_attr_occ_invert.attr,
> + Â Â Â &format_attr_occ_edge.attr,
> + Â Â Â NULL,
> +};
> +
> +static struct uncore_event_desc snbep_uncore_imc_events[] = {
> + Â Â Â INTEL_UNCORE_EVENT_DESC(CLOCKTICKS, "config=0xffff"),
> + Â Â Â /* read */
> + Â Â Â INTEL_UNCORE_EVENT_DESC(CAS_COUNT_RD, "event=0x4,umask=0x3"),
> + Â Â Â /* write */
> + Â Â Â INTEL_UNCORE_EVENT_DESC(CAS_COUNT_WR, "event=0x4,umask=0xc"),
> + Â Â Â { /* end: all zeroes */ },
> +};
> +
> +static struct uncore_event_desc snbep_uncore_qpi_events[] = {
> + Â Â Â INTEL_UNCORE_EVENT_DESC(CLOCKTICKS, "event=0x14"),
> + Â Â Â /* outgoing data+nondata flits */
> + Â Â Â INTEL_UNCORE_EVENT_DESC(TxL_FLITS_ACTIVE, "event=0x0,umask=0x6"),
> + Â Â Â /* DRS data received */
> + Â Â Â INTEL_UNCORE_EVENT_DESC(DRS_DATA, "event=0x2,umask=0x8"),
> + Â Â Â /* NCB data received */
> + Â Â Â INTEL_UNCORE_EVENT_DESC(NCB_DATA, "event=0x3,umask=0x4"),
> + Â Â Â { /* end: all zeroes */ },
> +};
> +
> +static struct attribute_group snbep_uncore_format_group = {
> + Â Â Â .name = "format",
> + Â Â Â .attrs = snbep_uncore_formats_attr,
> +};
> +
> +static struct attribute_group snbep_uncore_ubox_format_group = {
> + Â Â Â .name = "format",
> + Â Â Â .attrs = snbep_uncore_ubox_formats_attr,
> +};
> +
> +static struct attribute_group snbep_uncore_pcu_format_group = {
> + Â Â Â .name = "format",
> + Â Â Â .attrs = snbep_uncore_pcu_formats_attr,
> +};
> +
> +static struct intel_uncore_ops snbep_uncore_msr_ops = {
> +    .init_box    = snbep_uncore_msr_init_box,
> +    .disable_box  Â= snbep_uncore_msr_disable_box,
> +    .enable_box   = snbep_uncore_msr_enable_box,
> + Â Â Â .disable_event Â= snbep_uncore_msr_disable_event,
> +    .enable_event  = snbep_uncore_msr_enable_event,
> +    .read_counter  = snbep_uncore_msr_read_counter,
> +};
> +
> +static struct intel_uncore_ops snbep_uncore_pci_ops = {
> +    .init_box    = snbep_uncore_pci_init_box,
> +    .disable_box  Â= snbep_uncore_pci_disable_box,
> +    .enable_box   = snbep_uncore_pci_enable_box,
> + Â Â Â .disable_event Â= snbep_uncore_pci_disable_event,
> +    .enable_event  = snbep_uncore_pci_enable_event,
> +    .read_counter  = snbep_uncore_pci_read_counter,
> +};
> +
> +static struct event_constraint snbep_uncore_cbo_constraints[] = {
> + Â Â Â UNCORE_EVENT_CONSTRAINT(0x01, 0x1),
> + Â Â Â UNCORE_EVENT_CONSTRAINT(0x02, 0x3),
> + Â Â Â UNCORE_EVENT_CONSTRAINT(0x04, 0x3),
> + Â Â Â UNCORE_EVENT_CONSTRAINT(0x05, 0x3),
> + Â Â Â UNCORE_EVENT_CONSTRAINT(0x07, 0x3),
> + Â Â Â UNCORE_EVENT_CONSTRAINT(0x11, 0x1),
> + Â Â Â UNCORE_EVENT_CONSTRAINT(0x12, 0x3),
> + Â Â Â UNCORE_EVENT_CONSTRAINT(0x13, 0x3),
> + Â Â Â UNCORE_EVENT_CONSTRAINT(0x1b, 0xc),
> + Â Â Â UNCORE_EVENT_CONSTRAINT(0x1c, 0xc),
> + Â Â Â UNCORE_EVENT_CONSTRAINT(0x1d, 0xc),
> + Â Â Â UNCORE_EVENT_CONSTRAINT(0x1e, 0xc),
> + Â Â Â UNCORE_EVENT_CONSTRAINT(0x1f, 0xe),
> + Â Â Â UNCORE_EVENT_CONSTRAINT(0x21, 0x3),
> + Â Â Â UNCORE_EVENT_CONSTRAINT(0x23, 0x3),
> + Â Â Â UNCORE_EVENT_CONSTRAINT(0x31, 0x3),
> + Â Â Â UNCORE_EVENT_CONSTRAINT(0x32, 0x3),
> + Â Â Â UNCORE_EVENT_CONSTRAINT(0x33, 0x3),
> + Â Â Â UNCORE_EVENT_CONSTRAINT(0x34, 0x3),
> + Â Â Â UNCORE_EVENT_CONSTRAINT(0x35, 0x3),
> + Â Â Â UNCORE_EVENT_CONSTRAINT(0x36, 0x1),
> + Â Â Â UNCORE_EVENT_CONSTRAINT(0x37, 0x3),
> + Â Â Â UNCORE_EVENT_CONSTRAINT(0x38, 0x3),
> + Â Â Â UNCORE_EVENT_CONSTRAINT(0x39, 0x3),
> + Â Â Â UNCORE_EVENT_CONSTRAINT(0x3b, 0x1),
> + Â Â Â EVENT_CONSTRAINT_END
> +};
> +
> +static struct event_constraint snbep_uncore_r2pcie_constraints[] = {
> + Â Â Â UNCORE_EVENT_CONSTRAINT(0x10, 0x3),
> + Â Â Â UNCORE_EVENT_CONSTRAINT(0x11, 0x3),
> + Â Â Â UNCORE_EVENT_CONSTRAINT(0x12, 0x1),
> + Â Â Â UNCORE_EVENT_CONSTRAINT(0x23, 0x3),
> + Â Â Â UNCORE_EVENT_CONSTRAINT(0x24, 0x3),
> + Â Â Â UNCORE_EVENT_CONSTRAINT(0x25, 0x3),
> + Â Â Â UNCORE_EVENT_CONSTRAINT(0x26, 0x3),
> + Â Â Â UNCORE_EVENT_CONSTRAINT(0x32, 0x3),
> + Â Â Â UNCORE_EVENT_CONSTRAINT(0x33, 0x3),
> + Â Â Â UNCORE_EVENT_CONSTRAINT(0x34, 0x3),
> + Â Â Â EVENT_CONSTRAINT_END
> +};
> +
> +static struct event_constraint snbep_uncore_r3qpi_constraints[] = {
> + Â Â Â UNCORE_EVENT_CONSTRAINT(0x10, 0x3),
> + Â Â Â UNCORE_EVENT_CONSTRAINT(0x11, 0x3),
> + Â Â Â UNCORE_EVENT_CONSTRAINT(0x12, 0x3),
> + Â Â Â UNCORE_EVENT_CONSTRAINT(0x13, 0x1),
> + Â Â Â UNCORE_EVENT_CONSTRAINT(0x20, 0x3),
> + Â Â Â UNCORE_EVENT_CONSTRAINT(0x21, 0x3),
> + Â Â Â UNCORE_EVENT_CONSTRAINT(0x22, 0x3),
> + Â Â Â UNCORE_EVENT_CONSTRAINT(0x23, 0x3),
> + Â Â Â UNCORE_EVENT_CONSTRAINT(0x24, 0x3),
> + Â Â Â UNCORE_EVENT_CONSTRAINT(0x25, 0x3),
> + Â Â Â UNCORE_EVENT_CONSTRAINT(0x26, 0x3),
> + Â Â Â UNCORE_EVENT_CONSTRAINT(0x30, 0x3),
> + Â Â Â UNCORE_EVENT_CONSTRAINT(0x31, 0x3),
> + Â Â Â UNCORE_EVENT_CONSTRAINT(0x32, 0x3),
> + Â Â Â UNCORE_EVENT_CONSTRAINT(0x33, 0x3),
> + Â Â Â UNCORE_EVENT_CONSTRAINT(0x34, 0x3),
> + Â Â Â UNCORE_EVENT_CONSTRAINT(0x36, 0x3),
> + Â Â Â UNCORE_EVENT_CONSTRAINT(0x37, 0x3),
> + Â Â Â EVENT_CONSTRAINT_END
> +};
> +
> +static struct intel_uncore_type snbep_uncore_ubox = {
> +    .name      = "ubox",
> +    .num_counters  = 2,
> +    .num_boxes   Â= 1,
> + Â Â Â .perf_ctr_bits Â= 44,
> + Â Â Â .fixed_ctr_bits = 48,
> +    .perf_ctr    = SNBEP_U_MSR_PMON_CTR0,
> +    .event_ctl   Â= SNBEP_U_MSR_PMON_CTL0,
> +    .event_mask   = SNBEP_U_MSR_PMON_RAW_EVENT_MASK,
> +    .fixed_ctr   Â= SNBEP_U_MSR_PMON_UCLK_FIXED_CTR,
> +    .fixed_ctl   Â= SNBEP_U_MSR_PMON_UCLK_FIXED_CTL,
> +    .ops      Â= &snbep_uncore_msr_ops,
> +    .format_group  = &snbep_uncore_ubox_format_group,
> +};
> +
> +static struct intel_uncore_type snbep_uncore_cbo = {
> +    .name      = "cbo",
> +    .num_counters  = 4,
> +    .num_boxes   Â= 8,
> + Â Â Â .perf_ctr_bits Â= 44,
> +    .event_ctl   Â= SNBEP_C0_MSR_PMON_CTL0,
> +    .perf_ctr    = SNBEP_C0_MSR_PMON_CTR0,
> +    .event_mask   = SNBEP_PMON_RAW_EVENT_MASK,
> +    .box_ctl    Â= SNBEP_C0_MSR_PMON_BOX_CTL,
> +    .msr_offset   = SNBEP_CBO_MSR_OFFSET,
> +    .constraints  Â= snbep_uncore_cbo_constraints,
> +    .ops      Â= &snbep_uncore_msr_ops,
> +    .format_group  = &snbep_uncore_format_group,
> +};
> +
> +static struct intel_uncore_type snbep_uncore_pcu = {
> +    .name      = "pcu",
> +    .num_counters  = 4,
> +    .num_boxes   Â= 1,
> + Â Â Â .perf_ctr_bits Â= 48,
> +    .perf_ctr    = SNBEP_PCU_MSR_PMON_CTR0,
> +    .event_ctl   Â= SNBEP_PCU_MSR_PMON_CTL0,
> +    .event_mask   = SNBEP_PCU_MSR_PMON_RAW_EVENT_MASK,
> +    .box_ctl    Â= SNBEP_PCU_MSR_PMON_BOX_CTL,
> +    .ops      Â= &snbep_uncore_msr_ops,
> +    .format_group  = &snbep_uncore_pcu_format_group,
> +};
> +
> +static struct intel_uncore_type *snbep_msr_uncores[] = {
> + Â Â Â &snbep_uncore_ubox,
> + Â Â Â &snbep_uncore_cbo,
> + Â Â Â &snbep_uncore_pcu,
> + Â Â Â NULL,
> +};
> +
> +#define SNBEP_UNCORE_PCI_COMMON_INIT() Â Â Â Â Â Â Â Â Â Â Â Â \
> +    .perf_ctr    = SNBEP_PCI_PMON_CTR0,         Â\
> +    .event_ctl   Â= SNBEP_PCI_PMON_CTL0,         Â\
> +    .event_mask   = SNBEP_PMON_RAW_EVENT_MASK,      Â\
> +    .box_ctl    Â= SNBEP_PCI_PMON_BOX_CTL,        \
> +    .ops      Â= &snbep_uncore_pci_ops,        Â\
> +    .format_group  = &snbep_uncore_format_group
> +
> +static struct intel_uncore_type snbep_uncore_ha = {
> +    .name      = "ha",
> +    .num_counters  = 4,
> +    .num_boxes   Â= 1,
> + Â Â Â .perf_ctr_bits Â= 48,
> + Â Â Â SNBEP_UNCORE_PCI_COMMON_INIT(),
> +};
> +
> +static struct intel_uncore_type snbep_uncore_imc = {
> +    .name      = "imc",
> +    .num_counters  = 4,
> +    .num_boxes   Â= 4,
> + Â Â Â .perf_ctr_bits Â= 48,
> + Â Â Â .fixed_ctr_bits = 48,
> +    .fixed_ctr   Â= SNBEP_MC_CHy_PCI_PMON_FIXED_CTR,
> +    .fixed_ctl   Â= SNBEP_MC_CHy_PCI_PMON_FIXED_CTL,
> +    .event_descs  Â= snbep_uncore_imc_events,
> + Â Â Â SNBEP_UNCORE_PCI_COMMON_INIT(),
> +};
> +
> +static struct intel_uncore_type snbep_uncore_qpi = {
> +    .name      = "qpi",
> +    .num_counters  = 4,
> +    .num_boxes   Â= 2,
> + Â Â Â .perf_ctr_bits Â= 48,
> +    .event_descs  Â= snbep_uncore_qpi_events,
> + Â Â Â SNBEP_UNCORE_PCI_COMMON_INIT(),
> +};
> +
> +
> +static struct intel_uncore_type snbep_uncore_r2pcie = {
> +    .name      = "r2pcie",
> +    .num_counters  = 4,
> +    .num_boxes   Â= 1,
> + Â Â Â .perf_ctr_bits Â= 44,
> +    .constraints  Â= snbep_uncore_r2pcie_constraints,
> + Â Â Â SNBEP_UNCORE_PCI_COMMON_INIT(),
> +};
> +
> +static struct intel_uncore_type snbep_uncore_r3qpi = {
> +    .name      = "r3qpi",
> +    .num_counters  = 3,
> +    .num_boxes   Â= 2,
> + Â Â Â .perf_ctr_bits Â= 44,
> +    .constraints  Â= snbep_uncore_r3qpi_constraints,
> + Â Â Â SNBEP_UNCORE_PCI_COMMON_INIT(),
> +};
> +
> +static struct intel_uncore_type *snbep_pci_uncores[] = {
> + Â Â Â &snbep_uncore_ha,
> + Â Â Â &snbep_uncore_imc,
> + Â Â Â &snbep_uncore_qpi,
> + Â Â Â &snbep_uncore_r2pcie,
> + Â Â Â &snbep_uncore_r3qpi,
> + Â Â Â NULL,
> +};
> +
> +static DEFINE_PCI_DEVICE_TABLE(snbep_uncore_pci_ids) = {
> + Â Â Â { /* Home Agent */
> + Â Â Â Â Â Â Â PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_HA),
> + Â Â Â Â Â Â Â .driver_data = (unsigned long)&snbep_uncore_ha,
> + Â Â Â },
> + Â Â Â { /* MC Channel 0 */
> + Â Â Â Â Â Â Â PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_IMC0),
> + Â Â Â Â Â Â Â .driver_data = (unsigned long)&snbep_uncore_imc,
> + Â Â Â },
> + Â Â Â { /* MC Channel 1 */
> + Â Â Â Â Â Â Â PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_IMC1),
> + Â Â Â Â Â Â Â .driver_data = (unsigned long)&snbep_uncore_imc,
> + Â Â Â },
> + Â Â Â { /* MC Channel 2 */
> + Â Â Â Â Â Â Â PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_IMC2),
> + Â Â Â Â Â Â Â .driver_data = (unsigned long)&snbep_uncore_imc,
> + Â Â Â },
> + Â Â Â { /* MC Channel 3 */
> + Â Â Â Â Â Â Â PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_IMC3),
> + Â Â Â Â Â Â Â .driver_data = (unsigned long)&snbep_uncore_imc,
> + Â Â Â },
> + Â Â Â { /* QPI Port 0 */
> + Â Â Â Â Â Â Â PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_QPI0),
> + Â Â Â Â Â Â Â .driver_data = (unsigned long)&snbep_uncore_qpi,
> + Â Â Â },
> + Â Â Â { /* QPI Port 1 */
> + Â Â Â Â Â Â Â PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_QPI1),
> + Â Â Â Â Â Â Â .driver_data = (unsigned long)&snbep_uncore_qpi,
> + Â Â Â },
> + Â Â Â { /* P2PCIe */
> + Â Â Â Â Â Â Â PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_R2PCIE),
> + Â Â Â Â Â Â Â .driver_data = (unsigned long)&snbep_uncore_r2pcie,
> + Â Â Â },
> + Â Â Â { /* R3QPI Link 0 */
> + Â Â Â Â Â Â Â PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_R3QPI0),
> + Â Â Â Â Â Â Â .driver_data = (unsigned long)&snbep_uncore_r3qpi,
> + Â Â Â },
> + Â Â Â { /* R3QPI Link 1 */
> + Â Â Â Â Â Â Â PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_R3QPI1),
> + Â Â Â Â Â Â Â .driver_data = (unsigned long)&snbep_uncore_r3qpi,
> + Â Â Â },
> + Â Â Â { /* end: all zeroes */ }
> +};
> +
> +static struct pci_driver snbep_uncore_pci_driver = {
> +    .name      = "snbep_uncore",
> +    .id_table    = snbep_uncore_pci_ids,
> +};
> +
> +/*
> + * build pci bus to socket mapping
> + */
> +static void snbep_pci2phy_map_init(void)
> +{
> + Â Â Â struct pci_dev *ubox_dev = NULL;
> + Â Â Â int i, bus, nodeid;
> + Â Â Â u32 config;
> +
> + Â Â Â while (1) {
> + Â Â Â Â Â Â Â /* find the UBOX device */
> + Â Â Â Â Â Â Â ubox_dev = pci_get_device(PCI_VENDOR_ID_INTEL,
> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â PCI_DEVICE_ID_INTEL_JAKETOWN_UBOX,
> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â ubox_dev);
> + Â Â Â Â Â Â Â if (!ubox_dev)
> + Â Â Â Â Â Â Â Â Â Â Â break;
> + Â Â Â Â Â Â Â bus = ubox_dev->bus->number;
> + Â Â Â Â Â Â Â /* get the Node ID of the local register */
> + Â Â Â Â Â Â Â pci_read_config_dword(ubox_dev, 0x40, &config);
> + Â Â Â Â Â Â Â nodeid = config;
> + Â Â Â Â Â Â Â /* get the Node ID mapping */
> + Â Â Â Â Â Â Â pci_read_config_dword(ubox_dev, 0x54, &config);
> + Â Â Â Â Â Â Â /*
> + Â Â Â Â Â Â Â Â* every three bits in the Node ID mapping register maps
> + Â Â Â Â Â Â Â Â* to a particular node.
> + Â Â Â Â Â Â Â Â*/
> + Â Â Â Â Â Â Â for (i = 0; i < 8; i++) {
> + Â Â Â Â Â Â Â Â Â Â Â if (nodeid == ((config >> (3 * i)) & 0x7)) {
> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â pcibus_to_physid[bus] = i;
> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â break;
> + Â Â Â Â Â Â Â Â Â Â Â }
> + Â Â Â Â Â Â Â }
> + Â Â Â };
> + Â Â Â return;
> +}
> +/* end of Sandy Bridge-EP uncore support */
> +
>
> Â/* Sandy Bridge uncore support */
> Âstatic void snb_uncore_msr_enable_event(struct intel_uncore_box *box,
> @@ -894,6 +1370,11 @@ static int __init uncore_pci_init(void)
> Â Â Â Âint ret;
>
> Â Â Â Âswitch (boot_cpu_data.x86_model) {
> + Â Â Â case 45: /* Sandy Bridge-EP */
> + Â Â Â Â Â Â Â pci_uncores = snbep_pci_uncores;
> + Â Â Â Â Â Â Â uncore_pci_driver = &snbep_uncore_pci_driver;
> + Â Â Â Â Â Â Â snbep_pci2phy_map_init();
> + Â Â Â Â Â Â Â break;
> Â Â Â Âdefault:
> Â Â Â Â Â Â Â Âreturn 0;
> Â Â Â Â}
> @@ -1154,6 +1635,9 @@ static int __init uncore_cpu_init(void)
> Â Â Â Âcase 42: /* Sandy Bridge */
> Â Â Â Â Â Â Â Âmsr_uncores = snb_msr_uncores;
> Â Â Â Â Â Â Â Âbreak;
> + Â Â Â case 45: /* Sandy Birdge-EP */
> + Â Â Â Â Â Â Â msr_uncores = snbep_msr_uncores;
> + Â Â Â Â Â Â Â break;
> Â Â Â Âdefault:
> Â Â Â Â Â Â Â Âreturn 0;
> Â Â Â Â}
> diff --git a/arch/x86/kernel/cpu/perf_event_intel_uncore.h b/arch/x86/kernel/cpu/perf_event_intel_uncore.h
> index aa01df8..4d52db0 100644
> --- a/arch/x86/kernel/cpu/perf_event_intel_uncore.h
> +++ b/arch/x86/kernel/cpu/perf_event_intel_uncore.h
> @@ -65,6 +65,92 @@
> Â#define NHM_UNC_PERFEVTSEL0 Â Â Â Â Â Â Â Â Â Â 0x3c0
> Â#define NHM_UNC_UNCORE_PMC0 Â Â Â Â Â Â Â Â Â Â 0x3b0
>
> +/* SNB-EP Box level control */
> +#define SNBEP_PMON_BOX_CTL_RST_CTRL Â Â(1 << 0)
> +#define SNBEP_PMON_BOX_CTL_RST_CTRS Â Â(1 << 1)
> +#define SNBEP_PMON_BOX_CTL_FRZ Â Â Â Â (1 << 8)
> +#define SNBEP_PMON_BOX_CTL_FRZ_EN Â Â Â(1 << 16)
> +#define SNBEP_PMON_BOX_CTL_INT Â Â Â Â (SNBEP_PMON_BOX_CTL_RST_CTRL | \
> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â ÂSNBEP_PMON_BOX_CTL_RST_CTRS | \
> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â ÂSNBEP_PMON_BOX_CTL_FRZ_EN)
> +/* SNB-EP event control */
> +#define SNBEP_PMON_CTL_EV_SEL_MASK Â Â 0x000000ff
> +#define SNBEP_PMON_CTL_UMASK_MASK Â Â Â0x0000ff00
> +#define SNBEP_PMON_CTL_RST Â Â Â Â Â Â (1 << 17)
> +#define SNBEP_PMON_CTL_EDGE_DET Â Â Â Â Â Â Â Â(1 << 18)
> +#define SNBEP_PMON_CTL_EV_SEL_EXT Â Â Â(1 << 21) Â Â Â /* only for QPI */
> +#define SNBEP_PMON_CTL_EN Â Â Â Â Â Â Â(1 << 22)
> +#define SNBEP_PMON_CTL_INVERT Â Â Â Â Â(1 << 23)
> +#define SNBEP_PMON_CTL_TRESH_MASK Â Â Â0xff000000
> +#define SNBEP_PMON_RAW_EVENT_MASK Â Â Â(SNBEP_PMON_CTL_EV_SEL_MASK | \
> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â ÂSNBEP_PMON_CTL_UMASK_MASK | \
> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â ÂSNBEP_PMON_CTL_EDGE_DET | \
> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â ÂSNBEP_PMON_CTL_INVERT | \
> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â ÂSNBEP_PMON_CTL_TRESH_MASK)
> +
> +/* SNB-EP Ubox event control */
> +#define SNBEP_U_MSR_PMON_CTL_TRESH_MASK Â Â Â Â Â Â Â Â0x1f000000
> +#define SNBEP_U_MSR_PMON_RAW_EVENT_MASK Â Â Â Â Â Â Â Â\
> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â (SNBEP_PMON_CTL_EV_SEL_MASK | \
> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â ÂSNBEP_PMON_CTL_UMASK_MASK | \
> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â ÂSNBEP_PMON_CTL_EDGE_DET | \
> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â ÂSNBEP_PMON_CTL_INVERT | \
> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â ÂSNBEP_U_MSR_PMON_CTL_TRESH_MASK)
> +
> +/* SNB-EP PCU event control */
> +#define SNBEP_PCU_MSR_PMON_CTL_OCC_SEL_MASK Â Â0x0000c000
> +#define SNBEP_PCU_MSR_PMON_CTL_TRESH_MASK Â Â Â0x1f000000
> +#define SNBEP_PCU_MSR_PMON_CTL_OCC_INVERT Â Â Â(1 << 30)
> +#define SNBEP_PCU_MSR_PMON_CTL_OCC_EDGE_DET Â Â(1 << 31)
> +#define SNBEP_PCU_MSR_PMON_RAW_EVENT_MASK Â Â Â\
> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â (SNBEP_PMON_CTL_EV_SEL_MASK | \
> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â ÂSNBEP_PCU_MSR_PMON_CTL_OCC_SEL_MASK | \
> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â ÂSNBEP_PMON_CTL_EDGE_DET | \
> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â ÂSNBEP_PMON_CTL_INVERT | \
> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â ÂSNBEP_PCU_MSR_PMON_CTL_TRESH_MASK | \
> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â ÂSNBEP_PCU_MSR_PMON_CTL_OCC_INVERT | \
> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â ÂSNBEP_PCU_MSR_PMON_CTL_OCC_EDGE_DET)
> +
> +/* SNB-EP pci control register */
> +#define SNBEP_PCI_PMON_BOX_CTL Â Â Â Â Â Â Â Â 0xf4
> +#define SNBEP_PCI_PMON_CTL0 Â Â Â Â Â Â Â Â Â Â0xd8
> +/* SNB-EP pci counter register */
> +#define SNBEP_PCI_PMON_CTR0 Â Â Â Â Â Â Â Â Â Â0xa0
> +
> +/* SNB-EP home agent register */
> +#define SNBEP_HA_PCI_PMON_BOX_ADDRMATCH0 Â Â Â 0x40
> +#define SNBEP_HA_PCI_PMON_BOX_ADDRMATCH1 Â Â Â 0x44
> +#define SNBEP_HA_PCI_PMON_BOX_OPCODEMATCH Â Â Â0x48
> +/* SNB-EP memory controller register */
> +#define SNBEP_MC_CHy_PCI_PMON_FIXED_CTL Â Â Â Â Â Â Â Â0xf0
> +#define SNBEP_MC_CHy_PCI_PMON_FIXED_CTR Â Â Â Â Â Â Â Â0xd0
> +/* SNB-EP QPI register */
> +#define SNBEP_Q_Py_PCI_PMON_PKT_MATCH0 Â Â Â Â 0x228
> +#define SNBEP_Q_Py_PCI_PMON_PKT_MATCH1 Â Â Â Â 0x22c
> +#define SNBEP_Q_Py_PCI_PMON_PKT_MASK0 Â Â Â Â Â0x238
> +#define SNBEP_Q_Py_PCI_PMON_PKT_MASK1 Â Â Â Â Â0x23c
> +
> +/* SNB-EP Ubox register */
> +#define SNBEP_U_MSR_PMON_CTR0 Â Â Â Â Â Â Â Â Â0xc16
> +#define SNBEP_U_MSR_PMON_CTL0 Â Â Â Â Â Â Â Â Â0xc10
> +
> +#define SNBEP_U_MSR_PMON_UCLK_FIXED_CTL Â Â Â Â Â Â Â Â0xc08
> +#define SNBEP_U_MSR_PMON_UCLK_FIXED_CTR Â Â Â Â Â Â Â Â0xc09
> +
> +/* SNB-EP Cbo register */
> +#define SNBEP_C0_MSR_PMON_CTR0 Â Â Â Â Â Â Â Â 0xd16
> +#define SNBEP_C0_MSR_PMON_CTL0 Â Â Â Â Â Â Â Â 0xd10
> +#define SNBEP_C0_MSR_PMON_BOX_FILTER Â Â Â Â Â 0xd14
> +#define SNBEP_C0_MSR_PMON_BOX_CTL Â Â Â Â Â Â Â0xd04
> +#define SNBEP_CBO_MSR_OFFSET Â Â Â Â Â Â Â Â Â 0x20
> +
> +/* SNB-EP PCU register */
> +#define SNBEP_PCU_MSR_PMON_CTR0 Â Â Â Â Â Â Â Â Â Â Â Â0xc36
> +#define SNBEP_PCU_MSR_PMON_CTL0 Â Â Â Â Â Â Â Â Â Â Â Â0xc30
> +#define SNBEP_PCU_MSR_PMON_BOX_FILTER Â Â Â Â Â0xc34
> +#define SNBEP_PCU_MSR_PMON_BOX_CTL Â Â Â Â Â Â 0xc24
> +#define SNBEP_PCU_MSR_CORE_C3_CTR Â Â Â Â Â Â Â0x3fc
> +#define SNBEP_PCU_MSR_CORE_C6_CTR Â Â Â Â Â Â Â0x3fd
>
> Âstruct intel_uncore_ops;
> Âstruct intel_uncore_pmu;
> diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
> index 05fd02e..fc35260 100644
> --- a/include/linux/pci_ids.h
> +++ b/include/linux/pci_ids.h
> @@ -2756,6 +2756,17 @@
> Â#define PCI_DEVICE_ID_INTEL_IOAT_SNB7 Â0x3c27
> Â#define PCI_DEVICE_ID_INTEL_IOAT_SNB8 Â0x3c2e
> Â#define PCI_DEVICE_ID_INTEL_IOAT_SNB9 Â0x3c2f
> +#define PCI_DEVICE_ID_INTEL_UNC_HA Â Â 0x3c46
> +#define PCI_DEVICE_ID_INTEL_UNC_IMC0 Â 0x3cb0
> +#define PCI_DEVICE_ID_INTEL_UNC_IMC1 Â 0x3cb1
> +#define PCI_DEVICE_ID_INTEL_UNC_IMC2 Â 0x3cb4
> +#define PCI_DEVICE_ID_INTEL_UNC_IMC3 Â 0x3cb5
> +#define PCI_DEVICE_ID_INTEL_UNC_QPI0 Â 0x3c41
> +#define PCI_DEVICE_ID_INTEL_UNC_QPI1 Â 0x3c42
> +#define PCI_DEVICE_ID_INTEL_UNC_R2PCIE 0x3c43
> +#define PCI_DEVICE_ID_INTEL_UNC_R3QPI0 0x3c44
> +#define PCI_DEVICE_ID_INTEL_UNC_R3QPI1 0x3c45
> +#define PCI_DEVICE_ID_INTEL_JAKETOWN_UBOX Â Â Â0x3ce0
> Â#define PCI_DEVICE_ID_INTEL_IOAT_SNB Â 0x402f
> Â#define PCI_DEVICE_ID_INTEL_5100_16 Â Â0x65f0
> Â#define PCI_DEVICE_ID_INTEL_5100_21 Â Â0x65f5
> --
> 1.7.6.5
>
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