On 04/19/2012 09:27 PM, Laxman Dewangan wrote:On Thursday 19 April 2012 11:22 PM, Grant Grundler wrote:If the bit is cleared when reading the register I suppose it is not being worthOn Thu, Apr 19, 2012 at 4:15 AM, LaxmanRegister ADD_COMMAND1, bit 2 is interrupt flag bit which shows the
Dewangan<ldewangan@xxxxxxxxxx> wrote:
+static bool is_volatile_reg(struct device *dev, unsigned int reg)Of these four, I think only ADD_COMMAND1 wasn't treated as volatile in
+{
+ switch (reg) {
+ case ISL29018_REG_ADD_DATA_LSB:
+ case ISL29018_REG_ADD_DATA_MSB:
+ case ISL29018_REG_ADD_COMMAND1:
+ case ISL29018_REG_TEST:
the old code. Am I overlooking something?
My concern is only about the additional I2C read traffic this patch
might generate. It's possible *some* bits in that register are
volatile and we could previously ignore them.
interrupt status and hence we can not cache it.
The ISL29018 datasheet says:
Interrupt flag; Bit 2. This is the status bit of the interrupt.
The bit is set to logic high when the interrupt thresholds
have been triggered, and logic low when not yet triggered.
Once triggered, INT pin stays low and the status bit stays
high. Both interrupt pin and the status bit are automatically
cleared at the end of Command Register I transfer.
much to mark the register as volatile since the bit will be cleared whenever
you update the register. If there is only opmode and the irq bit in that
register I'd keep the register volatile, but use regmap_write instead of
regmap_update_bits.