RE: [PATCH v2] i2c: tegra: Add delay before reset the controller

[Alok Chauhan]

Stephen,

I've updated the commit message and comment in the code as per your suggestion. Tegra I2C controller doesn't have idle bit so delay is required before reset the controller in case of NACK error.  This delay is calculated purely based on clock period of that particular i2c bus and not passed as hardcoded value. I2C SCL clock-stretching won't affect this calculated delay.

Thanks
Alok


-----Original Message-----
From: Alok Chauhan [mailto:alokc@xxxxxxxxxx] 
Sent: Monday, April 02, 2012 11:23 AM
To: swarren@xxxxxxxxxxxxx; khali@xxxxxxxxxxxx; ben-linux@xxxxxxxxx; w.sang@xxxxxxxxxxxxxx; Stephen Warren; olof@xxxxxxxxx; bones@xxxxxxxxxxxx; omaplinuxkernel@xxxxxxxxx; ccross@xxxxxxxxxxx; Laxman Dewangan; linux-tegra@xxxxxxxxxxxxxxx; linux-i2c@xxxxxxxxxxxxxxx; dgreid@xxxxxxxxxxxx
Cc: Alok Chauhan; linux-kernel@xxxxxxxxxxxxxxx
Subject: [PATCH v2] i2c: tegra: Add delay before reset the controller

NACK interrupt generated before I2C controller generates the STOP condition on bus. In Software, because of this reset of controller is happening before I2C controller could complete STOP condition. So wait for some time before resetting the controller so that STOP condition has delivered properly on bus.

Added delay of 2 clock period before reset the controller in case of NACK error.

Signed-off-by: Alok Chauhan <alokc@xxxxxxxxxx>
---
Added the more descriptive commit message about issue in case of NACK error condition. Changed the comment in code also

 drivers/i2c/busses/i2c-tegra.c |    8 ++++++++
 1 files changed, 8 insertions(+), 0 deletions(-)

diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c index e978635..dfb850a8 100644
--- a/drivers/i2c/busses/i2c-tegra.c
+++ b/drivers/i2c/busses/i2c-tegra.c
@@ -516,6 +516,14 @@ static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev,
 	if (likely(i2c_dev->msg_err == I2C_ERR_NONE))
 		return 0;
 
+	/*
+	 * NACK interrupt generated before I2C controller generates the STOP
+	 * condition on bus. So wait for some time before reset the controller
+	 * so that STOP condition has delivered properly on bus.
+	 */
+	if (i2c_dev->msg_err == I2C_ERR_NO_ACK)
+		udelay(DIV_ROUND_UP(2 * 1000000, i2c_dev->bus_clk_rate));
+
 	tegra_i2c_init(i2c_dev);
 	if (i2c_dev->msg_err == I2C_ERR_NO_ACK) {
 		if (msg->flags & I2C_M_IGNORE_NAK)
--
1.7.4.1

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