Re: [PATCH 3/9] PCI: Disable cardbus bridge MEM1 pref CTL

[Jesse Barnes]

On Sat,  4 Feb 2012 22:55:02 -0800
Yinghai Lu <yinghai@xxxxxxxxxx> wrote:

> Some BIOS enable both pref for MEM0 and MEM1.
> 
> but we assume MEM1 is non-pref...
> 
> Signed-off-by: Yinghai Lu <yinghai@xxxxxxxxxx>
> ---
>  drivers/pci/setup-bus.c |    8 ++++++++
>  1 files changed, 8 insertions(+), 0 deletions(-)
> 
> diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c
> index 090217a..d5897c3 100644
> --- a/drivers/pci/setup-bus.c
> +++ b/drivers/pci/setup-bus.c
> @@ -914,6 +914,14 @@ static void pci_bus_size_cardbus(struct pci_bus *bus,
>  	if (realloc_head)
>  		add_to_list(realloc_head, bridge, b_res+1, pci_cardbus_io_size, 0 /* dont care */);
>  
> +	/* MEM1 must not be pref mmio */
> +	pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
> +	if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM1) {
> +		ctrl &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM1;
> +		pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl);
> +		pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
> +	}
> +
>  	/*
>  	 * Check whether prefetchable memory is supported
>  	 * by this bridge.

Does this actually fix any bugs?  Dominik, have you tested it?

Thanks,
-- 
Jesse Barnes, Intel Open Source Technology Center

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