RE: [PATCH v4 0/7] x86: BSP or CPU0 online/offline

[Luck, Tony]

> The question is, how realistically does this report true CPU 
> troubles, statistically? The on-die cache might have the highest 
> transistor count, but it's not under nearly the same thermal 
> stress as functional units.
>
> If 90% of all hard CPU failures can be predicted that way then 
> it's probably useful. If it's only 20%, then not so much.

Intel doesn't release error rates - so I can't help with data here.

> Also, it's still all theoretical until there's systems out there 
> where the CPU socket is physically hotpluggable. If there's such 
> plans in the works then sure, theory becomes reality and then 
> it's all useful - and then we can do these patches (and more).

No - physical removal of the cpu is not a requirement for this
to be useful.  If you have a system that is reporting cache
problems via the "yellow" status in the MCi_STATUS msr, then
there is benefit in simply soft off-lining the cores that share
that cache - assuming that leaves you some online cores! A single
socket system with L3 cache troubles is not helped - but problems
in L1/L2 cache, or on multi-socket systems can be avoided (and
are already being avoided for the cases where CPU0 is not involved).

Physical removal of the cpu is a problem for Linux since Nehalem
(when memory controller moved on-die). Take away the cpu, and you
lose access to the memory connected to that socket - and we don't
have general solutions for memory removal.

-Tony
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