Re: [PATCHv5] DMAEngine: Define interleaved transfer request api

[Vinod Koul]

On Fri, 2011-10-14 at 22:05 +0530, Jassi Brar wrote:
> >> and some hardwares need two seperate dma channels to tranfer left
> and
> >> right audio channel.
> >>
> >> For 1st and 2nd dma channel, they want dma address increases 4bytes
> >> and transfer 2bytes every line.
> >> so it looks to me like a cyclic interleaved dma.
> > Hmmm, do we have sound cards which use this?
> > Nevertheless for this kind of transfers we would need interleaved
> cyclic
> > DMA as well, Do you have such usage? Can you tell me which codec
> > requires this?
> >
> My proposed 'frm_irq' and 'cyclic' flags are for such requirements.
> 
> Consider a 5.1chan I2S controller that employs 3 dma-channels
> each transferring 2 audio-channels to 3 three FIFOs. And the
> pcm-dma driver supports SNDRV_PCM_INFO_INTERLEAVED.
> While I worked with simple single fifo 5.1chan I2S controllers, I
> don't
> think such 3-fifo controllers can't exist. 
I am not against cyclic, and yes 3 fifos can exist but one would
question why we need 3 controller, 3 sets of ports and pins and
associated analog stuff when one can do with one :)

Nevertheless, cyclic should be supported for all dmaengine APIs (but not
adding new APIs for cyclic) and in consistent manner by having a generic
cyclic flag and caps.

-- 
~Vinod

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