Re: Workaround for Intel MPS errata

[Avi Kivity]

On 10/03/2011 05:12 PM, Jon Mason wrote:
>      PCI: Workaround for Intel MPS errata
>
>      Intel 5000 and 5100 series memory controllers have a known issue if read
>      completion coalescing is enabled (the default setting) and the PCI-E
>      Maximum Payload Size is set to 256B.  To work around this issue, disable
>      read completion coalescing if the MPS is 256B.
>
>      It is worth noting that there is no function to undo the disable of read
>      completion coalescing, and the performance benefit of read completion
>      coalescing will be lost if the MPS is set from 256B to 128B.  It is only
>      possible to have this issue via hotplug removing the only 256B MPS
>      device in the system (thus making all of the other devices in the system
>      have a performance degradation without the benefit of any 256B
>      transfers).  Therefore, this trade off is acceptable.
>
>      http://www.intel.com/content/dam/doc/specification-update/5000-chipset-memory-controller-hub-specification-update.pdf
>      http://www.intel.com/content/dam/doc/specification-update/5100-memory-controller-hub-chipset-specification-update.pdf
>
>      Thanks to Jesse Brandeburg and Ben Hutchings for providing insight into
>      the problem.
>
>      Reported-by: Avi Kivity<avi@xxxxxxxxxx>
>      Signed-off-by: Jon Mason<mason@xxxxxxxx>
>
> +
> +		if (!(val&  (1<<  10))) {
> +			done = true;
> +			return;
> +		}

Here, you bail out if bit 10 is clear.  So if we're here, it's set.

> +
> +		val |= (1<<  10);

Now it's even more set?

> +		err = pci_bus_write_config_word(bus, 0, 0x48, val);
> +		if (err) {
> +			dev_err(&bus->dev, "Error attempting to write the read "
> +				"completion coalescing register.\n");
> +			return;
> +		}
> +
> +		dev_info(&bus->dev, "Read completion coalescing disabled due "
> +			 "to hardware errata relating to 256B MPS.\n");
> +
> +		done = true;
> +	}
> +}
> +

--
error compiling committee.c: too many arguments to function

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