Re: [PATCH v2] perf, x86: Fix event scheduler for constraints withoverlapping counters

From: Robert Richter
Date: Thu Sep 01 2011 - 10:12:36 EST


On 01.09.11 08:56:46, Peter Zijlstra wrote:
> On Fri, 2011-05-20 at 05:18 +0200, Robert Richter wrote:
> > On 19.05.11 14:06:50, Ingo Molnar wrote:
> > > * Peter Zijlstra <peterz@xxxxxxxxxxxxx> wrote:
> > >
> > > > On Wed, 2011-05-18 at 23:20 +0200, Ingo Molnar wrote:
> > > > > * Peter Zijlstra <peterz@xxxxxxxxxxxxx> wrote:
> > > > >
> > > > > > > if (c->weight != w)
> > > > > > > continue;
> > > > > > >
> > > > > > > - for_each_set_bit(j, c->idxmsk, X86_PMC_IDX_MAX) {
> > > > > > > - if (!test_bit(j, used_mask))
> > > > > > > + /* for each bit in idxmsk starting from idx */
> > > > > > > + while (idx < X86_PMC_IDX_MAX) {
> > > > > > > + idx = find_next_bit(c->idxmsk, X86_PMC_IDX_MAX,
> > > > > > > + idx);
> > > > > >
> > > > > > I'd be mighty tempted to ignore that 80 column rule here ;-)
> > > > >
> > > > > Please put the body of the loop into a helper function, the function is large
> > > > > and there are countless col80 uglinesses in it!
> > > >
> > > > I just tried that, its real ugly due to the amount of state you need to
> > > > pass around.
> > >
> > > Does it help if you put that state into a helper structure?
> >
> > Yes, this is what I have in mind too. We could iterate on such a state
> > stucture instead of a couple of single variables. Storing and
> > restoring the state will then just copying the structure.
>
> Any word on this work? I just noticed we actually need this for Intel
> too, the fixed purpose events have overlapping but non-identical
> constraint masks.
>
> Now we could optimize the Intel case by always iterating from the top
> down, but it won't cure all cases. For example, suppose one counter
> (that could be on a FP reg) previously got scheduled on a GP register
> and we take the fast-path, in that case we would still end up
> under-utilized.

Yes, I had this patch in mind too. Will try to post an updated version
next week. Ok?

-Robert

--
Advanced Micro Devices, Inc.
Operating System Research Center

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