There is no need to determine it by calculating, because it caused by the special design of the BD L1 cache and thus fixed.
And a calculation would be even more confusing:
The L1I is virtually indexed, but physically tagged.
64KB L1I cache, 64 Bytes per Cacheline = 1024 cache lines
1024 lines / 2 way associative = 512 indexes
64 Bytes per Cacheline (6 bits) + 512 indexes (9 bits) = bits [14:0]
virtual and physical addresses are the same for bits [11:0], which leaves the remaining 14:12 susceptible for aliasing.
So bit 12 comes from PAGESIZE and yes, the 14 could be derived from the CPUID cache info, but I don't see much value in breaking this down this way.
But I agree that there should be some comment in the patch which at least notes that bits [14:12] are due to the L1I design, maybe we can copy a nicer version of the above math in the commit message for reference.