Re: [PATCH] cpu, AMD: Fix another bug in the new errata checkingcode

[Boris Ostrovsky]

On 05/13/2011 06:21 AM, Hans Rosenfeld wrote:
> On Thu, May 12, 2011 at 07:59:38PM -0400, Chuck Ebbert wrote:
> The revision guide states that family 0x10 model 6 stepping 2 has E400.
> So I would expect that OSVW length is>= 2 and that OSVW status has bit
> 1 set, or that OSVW length is<  2. This indicates that the workaround is
> necessary, without any need to check the family-model-stepping ranges.
>
> It would also be correct if the BIOS disabled C1E and cleared the
> corresponding OSVW status bit. Anything else would probably be a very
> nasty BIOS bug.
>
> Could you send me the contents of MSRs 0xc0010140, 0xc0010141 and
> 0xc0010055?

Knowing whether any C state above C1 is declared could be useful too.

-boris

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