Re: [PATCH v2 -tip] perf: x86, add SandyBridge support

From: Stephane Eranian
Date: Mon Feb 28 2011 - 03:20:20 EST

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On Mon, Feb 28, 2011 at 8:22 AM, Lin Ming <ming.m.lin@xxxxxxxxx> wrote:
> This patch adds basic SandyBridge support, including hardware cache
> events and PEBS events support.
>
> LLC-* hareware cache events don't work for now, it depends on the
> offcore patches.
>
> All PEBS events are tested on my SandyBridge machine and work well.
> Note that SandyBridge does not support INSTR_RETIRED.ANY(0x00c0) PEBS
> event, instead it supports INST_RETIRED.PRECDIST(0x01c0) event and PMC1
> only.
>
> v1 -> v2:
> - add more raw and PEBS events constraints
> - use offcore events for LLC-* cache events
> - remove the call to Nehalem workaround enable_all function
>
> todo:
> - precise store
> - precise distribution of instructions retired
>
> Signed-off-by: Lin Ming <ming.m.lin@xxxxxxxxx>
> ---
> Âarch/x86/kernel/cpu/perf_event.c Â Â Â Â Â| Â Â2 +
> Âarch/x86/kernel/cpu/perf_event_intel.c Â Â| Â123 +++++++++++++++++++++++++++++
> Âarch/x86/kernel/cpu/perf_event_intel_ds.c | Â 44 ++++++++++-
> Â3 files changed, 168 insertions(+), 1 deletions(-)
>
> diff --git a/arch/x86/kernel/cpu/perf_event.c b/arch/x86/kernel/cpu/perf_event.c
> index 10bfe24..49d51be 100644
> --- a/arch/x86/kernel/cpu/perf_event.c
> +++ b/arch/x86/kernel/cpu/perf_event.c
> @@ -148,6 +148,8 @@ struct cpu_hw_events {
> Â*/
> Â#define INTEL_EVENT_CONSTRAINT(c, n) Â \
> Â Â Â ÂEVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT)
> +#define INTEL_EVENT_CONSTRAINT2(c, n) Â\
> + Â Â Â EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK)
>
> Â/*
> Â* Constraint on the Event code + UMask + fixed-mask
> diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
> index 084b383..3085868 100644
> --- a/arch/x86/kernel/cpu/perf_event_intel.c
> +++ b/arch/x86/kernel/cpu/perf_event_intel.c
> @@ -76,6 +76,19 @@ static struct event_constraint intel_westmere_event_constraints[] =
> Â Â Â ÂEVENT_CONSTRAINT_END
> Â};
>
> +static struct event_constraint intel_snb_event_constraints[] =
> +{
> + Â Â Â FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
> + Â Â Â FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
> + Â Â Â /* FIXED_EVENT_CONSTRAINT(0x013c, 2), CPU_CLK_UNHALTED.REF */
> + Â Â Â INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */
> + Â Â Â INTEL_EVENT_CONSTRAINT(0xb7, 0x1), /* OFF_CORE_RESPONSE_0 */
> + Â Â Â INTEL_EVENT_CONSTRAINT(0xbb, 0x8), /* OFF_CORE_RESPONSE_1 */
> + Â Â Â INTEL_EVENT_CONSTRAINT2(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
> + Â Â Â INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
> + Â Â Â EVENT_CONSTRAINT_END
> +};
> +
> Âstatic struct event_constraint intel_gen_event_constraints[] =
> Â{
> Â Â Â ÂFIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
> @@ -89,6 +102,106 @@ static u64 intel_pmu_event_map(int hw_event)
> Â Â Â Âreturn intel_perfmon_event_map[hw_event];
> Â}
>
> +static __initconst const u64 snb_hw_cache_event_ids
> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â [PERF_COUNT_HW_CACHE_MAX]
> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â [PERF_COUNT_HW_CACHE_OP_MAX]
> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â [PERF_COUNT_HW_CACHE_RESULT_MAX] =
> +{
> + [ C(L1D) ] = {
> + Â Â Â [ C(OP_READ) ] = {
> + Â Â Â Â Â Â Â [ C(RESULT_ACCESS) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS Â Â Â Â*/
> + Â Â Â Â Â Â Â [ C(RESULT_MISS) Â ] = 0x0151, /* L1D.REPLACEMENT Â Â Â Â Â Â Â*/
> + Â Â Â },
> + Â Â Â [ C(OP_WRITE) ] = {
> + Â Â Â Â Â Â Â [ C(RESULT_ACCESS) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES Â Â Â */
> + Â Â Â Â Â Â Â [ C(RESULT_MISS) Â ] = 0x0851, /* L1D.ALL_M_REPLACEMENT Â Â Â Â*/
> + Â Â Â },
> + Â Â Â [ C(OP_PREFETCH) ] = {
> + Â Â Â Â Â Â Â [ C(RESULT_ACCESS) ] = 0x0,
> + Â Â Â Â Â Â Â [ C(RESULT_MISS) Â ] = 0x024e, /* HW_PRE_REQ.DL1_MISS Â Â Â Â Â*/
> + Â Â Â },
> + },
> + [ C(L1I ) ] = {
> + Â Â Â [ C(OP_READ) ] = {
> + Â Â Â Â Â Â Â [ C(RESULT_ACCESS) ] = 0x0,
> + Â Â Â Â Â Â Â [ C(RESULT_MISS) Â ] = 0x0280, /* ICACHE.MISSES */
> + Â Â Â },
> + Â Â Â [ C(OP_WRITE) ] = {
> + Â Â Â Â Â Â Â [ C(RESULT_ACCESS) ] = -1,
> + Â Â Â Â Â Â Â [ C(RESULT_MISS) Â ] = -1,
> + Â Â Â },
> + Â Â Â [ C(OP_PREFETCH) ] = {
> + Â Â Â Â Â Â Â [ C(RESULT_ACCESS) ] = 0x0,
> + Â Â Â Â Â Â Â [ C(RESULT_MISS) Â ] = 0x0,
> + Â Â Â },
> + },
> + [ C(LL Â) ] = {
> + Â Â Â /*
> + Â Â Â Â* TBD: Need Off-core Response Performance Monitoring support
> + Â Â Â Â*/
> + Â Â Â [ C(OP_READ) ] = {
> + Â Â Â Â Â Â Â /* OFFCORE_RESPONSE_0.ANY_DATA.LOCAL_CACHE */
> + Â Â Â Â Â Â Â [ C(RESULT_ACCESS) ] = 0x01b7,
> + Â Â Â Â Â Â Â /* OFFCORE_RESPONSE_1.ANY_DATA.ANY_LLC_MISS */
> + Â Â Â Â Â Â Â [ C(RESULT_MISS) Â ] = 0x01bb,
> + Â Â Â },
> + Â Â Â [ C(OP_WRITE) ] = {
> + Â Â Â Â Â Â Â /* OFFCORE_RESPONSE_0.ANY_RFO.LOCAL_CACHE */
> + Â Â Â Â Â Â Â [ C(RESULT_ACCESS) ] = 0x01b7,
> + Â Â Â Â Â Â Â /* OFFCORE_RESPONSE_1.ANY_RFO.ANY_LLC_MISS */
> + Â Â Â Â Â Â Â [ C(RESULT_MISS) Â ] = 0x01bb,
> + Â Â Â },
> + Â Â Â [ C(OP_PREFETCH) ] = {
> + Â Â Â Â Â Â Â /* OFFCORE_RESPONSE_0.PREFETCH.LOCAL_CACHE */
> + Â Â Â Â Â Â Â [ C(RESULT_ACCESS) ] = 0x01b7,
> + Â Â Â Â Â Â Â /* OFFCORE_RESPONSE_1.PREFETCH.ANY_LLC_MISS */
> + Â Â Â Â Â Â Â [ C(RESULT_MISS) Â ] = 0x01bb,
> + Â Â Â },
> + },
> + [ C(DTLB) ] = {
> + Â Â Â [ C(OP_READ) ] = {
> + Â Â Â Â Â Â Â [ C(RESULT_ACCESS) ] = 0x01d0, /* MEM_UOP_RETIRED.LOADS */
> + Â Â Â Â Â Â Â [ C(RESULT_MISS) Â ] = 0x0108, /* DTLB_LOAD_MISSES.CAUSES_A_WALK */
> + Â Â Â },
> + Â Â Â [ C(OP_WRITE) ] = {
> + Â Â Â Â Â Â Â [ C(RESULT_ACCESS) ] = 0x02d0, /* MEM_UOP_RETIRED.STORES */
> + Â Â Â Â Â Â Â [ C(RESULT_MISS) Â ] = 0x0149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
> + Â Â Â },
> + Â Â Â [ C(OP_PREFETCH) ] = {
> + Â Â Â Â Â Â Â [ C(RESULT_ACCESS) ] = 0x0,
> + Â Â Â Â Â Â Â [ C(RESULT_MISS) Â ] = 0x0,
> + Â Â Â },
> + },
> + [ C(ITLB) ] = {
> + Â Â Â [ C(OP_READ) ] = {
> + Â Â Â Â Â Â Â [ C(RESULT_ACCESS) ] = 0x1085, /* ITLB_MISSES.STLB_HIT Â Â Â Â */
> + Â Â Â Â Â Â Â [ C(RESULT_MISS) Â ] = 0x0185, /* ITLB_MISSES.CAUSES_A_WALK Â Â*/
> + Â Â Â },
> + Â Â Â [ C(OP_WRITE) ] = {
> + Â Â Â Â Â Â Â [ C(RESULT_ACCESS) ] = -1,
> + Â Â Â Â Â Â Â [ C(RESULT_MISS) Â ] = -1,
> + Â Â Â },
> + Â Â Â [ C(OP_PREFETCH) ] = {
> + Â Â Â Â Â Â Â [ C(RESULT_ACCESS) ] = -1,
> + Â Â Â Â Â Â Â [ C(RESULT_MISS) Â ] = -1,
> + Â Â Â },
> + },
> + [ C(BPU ) ] = {
> + Â Â Â [ C(OP_READ) ] = {
> + Â Â Â Â Â Â Â [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
> + Â Â Â Â Â Â Â [ C(RESULT_MISS) Â ] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
> + Â Â Â },
> + Â Â Â [ C(OP_WRITE) ] = {
> + Â Â Â Â Â Â Â [ C(RESULT_ACCESS) ] = -1,
> + Â Â Â Â Â Â Â [ C(RESULT_MISS) Â ] = -1,
> + Â Â Â },
> + Â Â Â [ C(OP_PREFETCH) ] = {
> + Â Â Â Â Â Â Â [ C(RESULT_ACCESS) ] = -1,
> + Â Â Â Â Â Â Â [ C(RESULT_MISS) Â ] = -1,
> + Â Â Â },
> + },
> +};
> +
> Âstatic __initconst const u64 westmere_hw_cache_event_ids
> Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â[PERF_COUNT_HW_CACHE_MAX]
> Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â[PERF_COUNT_HW_CACHE_OP_MAX]
> @@ -1062,6 +1175,16 @@ static __init int intel_pmu_init(void)
> Â Â Â Â Â Â Â Âpr_cont("Westmere events, ");
> Â Â Â Â Â Â Â Âbreak;
>
> + Â Â Â case 42: /* SandyBridge */
> + Â Â Â Â Â Â Â memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
> + Â Â Â Â Â Â Â Â Â Â Âsizeof(hw_cache_event_ids));
> +
> + Â Â Â Â Â Â Â intel_pmu_lbr_init_nhm();
> +
> + Â Â Â Â Â Â Â x86_pmu.event_constraints = intel_snb_event_constraints;
> + Â Â Â Â Â Â Â pr_cont("SandyBridge events, ");
> + Â Â Â Â Â Â Â break;
> +
> Â Â Â Âdefault:
> Â Â Â Â Â Â Â Â/*
> Â Â Â Â Â Â Â Â * default constraints for v2 and up
> diff --git a/arch/x86/kernel/cpu/perf_event_intel_ds.c b/arch/x86/kernel/cpu/perf_event_intel_ds.c
> index b7dcd9f..e60f91b 100644
> --- a/arch/x86/kernel/cpu/perf_event_intel_ds.c
> +++ b/arch/x86/kernel/cpu/perf_event_intel_ds.c
> @@ -388,6 +388,42 @@ static struct event_constraint intel_nehalem_pebs_events[] = {
> Â Â Â ÂEVENT_CONSTRAINT_END
> Â};
>
> +static struct event_constraint intel_snb_pebs_events[] = {
> + Â Â Â PEBS_EVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
> + Â Â Â PEBS_EVENT_CONSTRAINT(0x01c2, 0xf), /* UOPS_RETIRED.ALL */
> + Â Â Â PEBS_EVENT_CONSTRAINT(0x02c2, 0xf), /* UOPS_RETIRED.RETIRE_SLOTS */
> + Â Â Â PEBS_EVENT_CONSTRAINT(0x01c4, 0xf), /* BR_INST_RETIRED.CONDITIONAL */
> + Â Â Â PEBS_EVENT_CONSTRAINT(0x02c4, 0xf), /* BR_INST_RETIRED.NEAR_CALL */
> + Â Â Â PEBS_EVENT_CONSTRAINT(0x04c4, 0xf), /* BR_INST_RETIRED.ALL_BRANCHES */
> + Â Â Â PEBS_EVENT_CONSTRAINT(0x08c4, 0xf), /* BR_INST_RETIRED.NEAR_RETURN */
> + Â Â Â PEBS_EVENT_CONSTRAINT(0x10c4, 0xf), /* BR_INST_RETIRED.NOT_TAKEN */
> + Â Â Â PEBS_EVENT_CONSTRAINT(0x20c4, 0xf), /* BR_INST_RETIRED.NEAR_TAKEN */
> + Â Â Â PEBS_EVENT_CONSTRAINT(0x40c4, 0xf), /* BR_INST_RETIRED.FAR_BRANCH */
> + Â Â Â PEBS_EVENT_CONSTRAINT(0x01c5, 0xf), /* BR_MISP_RETIRED.CONDITIONAL */
> + Â Â Â PEBS_EVENT_CONSTRAINT(0x02c5, 0xf), /* BR_MISP_RETIRED.NEAR_CALL */
> + Â Â Â PEBS_EVENT_CONSTRAINT(0x04c5, 0xf), /* BR_MISP_RETIRED.ALL_BRANCHES */
> + Â Â Â PEBS_EVENT_CONSTRAINT(0x10c5, 0xf), /* BR_MISP_RETIRED.NOT_TAKEN */
> + Â Â Â PEBS_EVENT_CONSTRAINT(0x20c5, 0xf), /* BR_MISP_RETIRED.TAKEN */
> + Â Â Â PEBS_EVENT_CONSTRAINT(0x01cd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
> + Â Â Â PEBS_EVENT_CONSTRAINT(0x02cd, 0x8), /* MEM_TRANS_RETIRED.PRECISE_STORE */

> + Â Â Â PEBS_EVENT_CONSTRAINT(0x01d0, 0xf), /* MEM_UOP_RETIRED.LOADS */
> + Â Â Â PEBS_EVENT_CONSTRAINT(0x02d0, 0xf), /* MEM_UOP_RETIRED.STORES */
> + Â Â Â PEBS_EVENT_CONSTRAINT(0x10d0, 0xf), /* MEM_UOP_RETIRED.STLB_MISS */
> + Â Â Â PEBS_EVENT_CONSTRAINT(0x20d0, 0xf), /* MEM_UOP_RETIRED.LOCK */
> + Â Â Â PEBS_EVENT_CONSTRAINT(0x40d0, 0xf), /* MEM_UOP_RETIRED.SPLIT */
> + Â Â Â PEBS_EVENT_CONSTRAINT(0x80d0, 0xf), /* MEM_UOP_RETIRED.ALL */

Not quite. For event 0xd0, you are not listing the right umask combinations.
The following combinations are supported for event 0xd0:

0x5381d0 snb::MEM_UOP_RETIRED:ANY_LOADS
0x5382d0 snb::MEM_UOP_RETIRED:ANY_STORES
0x5321d0 snb::MEM_UOP_RETIRED:LOCK_LOADS
0x5322d0 snb::MEM_UOP_RETIRED:LOCK_STORES
0x5341d0 snb::MEM_UOP_RETIRED:SPLIT_LOADS
0x5342d0 snb::MEM_UOP_RETIRED:SPLIT_STORES
0x5311d0 snb::MEM_UOP_RETIRED:STLB_MISS_LOADS
0x5312d0 snb::MEM_UOP_RETIRED:STLB_MISS_STORES

In other words, bit 0-3 of the umask cannot be zero.
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Next message: tip-bot for Thomas Renninger: "[tip:perf/urgent] perf timechart: Fix black idle boxes in the title"
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In reply to: Lin Ming: "[PATCH v2 -tip] perf: x86, add SandyBridge support"
Next in thread: Lin Ming: "Re: [PATCH v2 -tip] perf: x86, add SandyBridge support"
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