Re: [PATCH -tip] perf: x86, add SandyBridge support

[Stephane Eranian]

Lin,

On Thu, Feb 24, 2011 at 2:59 PM, Lin Ming <ming.m.lin@xxxxxxxxx> wrote:
> Adds SandyBridge support to perf.
>
> Signed-off-by: Lin Ming <ming.m.lin@xxxxxxxxx>
> ---
> Âarch/x86/kernel/cpu/perf_event_intel.c | Â111 ++++++++++++++++++++++++++++++++
> Â1 files changed, 111 insertions(+), 0 deletions(-)
>
> diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
> index 084b383..4a132c9 100644
> --- a/arch/x86/kernel/cpu/perf_event_intel.c
> +++ b/arch/x86/kernel/cpu/perf_event_intel.c
> @@ -76,6 +76,15 @@ static struct event_constraint intel_westmere_event_constraints[] =
> Â Â Â ÂEVENT_CONSTRAINT_END
> Â};
>
> +static struct event_constraint intel_snb_event_constraints[] =
> +{
> + Â Â Â FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
> + Â Â Â FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
> + Â Â Â /* FIXED_EVENT_CONSTRAINT(0x013c, 2), CPU_CLK_UNHALTED.REF */
> + Â Â Â INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */
> + Â Â Â EVENT_CONSTRAINT_END
> +};
> +

There are more constraints than these, unfortunately. I have been
trying to get Intel
to make them public...

> Âstatic struct event_constraint intel_gen_event_constraints[] =
> Â{
> Â Â Â ÂFIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
> @@ -89,6 +98,97 @@ static u64 intel_pmu_event_map(int hw_event)
> Â Â Â Âreturn intel_perfmon_event_map[hw_event];
> Â}
>
> +static __initconst const u64 snb_hw_cache_event_ids
> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â [PERF_COUNT_HW_CACHE_MAX]
> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â [PERF_COUNT_HW_CACHE_OP_MAX]
> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â [PERF_COUNT_HW_CACHE_RESULT_MAX] =
> +{
> + [ C(L1D) ] = {
> + Â Â Â [ C(OP_READ) ] = {
> + Â Â Â Â Â Â Â [ C(RESULT_ACCESS) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS Â Â Â Â*/
> + Â Â Â Â Â Â Â [ C(RESULT_MISS) Â ] = 0x0151, /* L1D.REPLACEMENT Â Â Â Â Â Â Â*/
> + Â Â Â },
> + Â Â Â [ C(OP_WRITE) ] = {
> + Â Â Â Â Â Â Â [ C(RESULT_ACCESS) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES Â Â Â */
> + Â Â Â Â Â Â Â [ C(RESULT_MISS) Â ] = 0x0851, /* L1D.ALL_M_REPLACEMENT Â Â Â Â*/
> + Â Â Â },
> + Â Â Â [ C(OP_PREFETCH) ] = {
> + Â Â Â Â Â Â Â [ C(RESULT_ACCESS) ] = 0x0,
> + Â Â Â Â Â Â Â [ C(RESULT_MISS) Â ] = 0x024e, /* HW_PRE_REQ.DL1_MISS Â Â Â Â Â*/
> + Â Â Â },
> + },
> + [ C(L1I ) ] = {
> + Â Â Â [ C(OP_READ) ] = {
> + Â Â Â Â Â Â Â [ C(RESULT_ACCESS) ] = 0x0,
> + Â Â Â Â Â Â Â [ C(RESULT_MISS) Â ] = 0x0280, /* ICACHE.MISSES */
> + Â Â Â },
> + Â Â Â [ C(OP_WRITE) ] = {
> + Â Â Â Â Â Â Â [ C(RESULT_ACCESS) ] = -1,
> + Â Â Â Â Â Â Â [ C(RESULT_MISS) Â ] = -1,
> + Â Â Â },
> + Â Â Â [ C(OP_PREFETCH) ] = {
> + Â Â Â Â Â Â Â [ C(RESULT_ACCESS) ] = 0x0,
> + Â Â Â Â Â Â Â [ C(RESULT_MISS) Â ] = 0x0,
> + Â Â Â },
> + },
> + [ C(LL Â) ] = {
> + Â Â Â [ C(OP_READ) ] = {
> + Â Â Â Â Â Â Â [ C(RESULT_ACCESS) ] = 0x04d1, /* MEM_LOAD_UOPS_RETIRED.LLC_HIT */
> + Â Â Â Â Â Â Â [ C(RESULT_MISS) Â ] = 0x0,
> + Â Â Â },
> + Â Â Â [ C(OP_WRITE) ] = {
> + Â Â Â Â Â Â Â [ C(RESULT_ACCESS) ] = 0x0424, /* L2_RQSTS.RFO_HITS */
> + Â Â Â Â Â Â Â [ C(RESULT_MISS) Â ] = 0x0824, /* L2_RQSTS.RFO_MISS */
> + Â Â Â },
> + Â Â Â [ C(OP_PREFETCH) ] = {
> + Â Â Â Â Â Â Â [ C(RESULT_ACCESS) ] = 0x4f2e, /* L3_LAT_CACHE.REFERENCE Â Â Â */
> + Â Â Â Â Â Â Â [ C(RESULT_MISS) Â ] = 0x412e, /* L3_LAT_CACHE.MISS Â Â Â Â Â Â*/
> + Â Â Â },
> + },
> + [ C(DTLB) ] = {
> + Â Â Â [ C(OP_READ) ] = {
> + Â Â Â Â Â Â Â [ C(RESULT_ACCESS) ] = 0x01d0, /* MEM_UOP_RETIRED.LOADS */
> + Â Â Â Â Â Â Â [ C(RESULT_MISS) Â ] = 0x0108, /* DTLB_LOAD_MISSES.CAUSES_A_WALK */
> + Â Â Â },
> + Â Â Â [ C(OP_WRITE) ] = {
> + Â Â Â Â Â Â Â [ C(RESULT_ACCESS) ] = 0x02d0, /* MEM_UOP_RETIRED.STORES */
> + Â Â Â Â Â Â Â [ C(RESULT_MISS) Â ] = 0x0149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
> + Â Â Â },
> + Â Â Â [ C(OP_PREFETCH) ] = {
> + Â Â Â Â Â Â Â [ C(RESULT_ACCESS) ] = 0x0,
> + Â Â Â Â Â Â Â [ C(RESULT_MISS) Â ] = 0x0,
> + Â Â Â },
> + },
> + [ C(ITLB) ] = {
> + Â Â Â [ C(OP_READ) ] = {
> + Â Â Â Â Â Â Â [ C(RESULT_ACCESS) ] = 0x1085, /* ITLB_MISSES.STLB_HIT Â Â Â Â */
> + Â Â Â Â Â Â Â [ C(RESULT_MISS) Â ] = 0x0185, /* ITLB_MISSES.CAUSES_A_WALK Â Â*/
> + Â Â Â },
> + Â Â Â [ C(OP_WRITE) ] = {
> + Â Â Â Â Â Â Â [ C(RESULT_ACCESS) ] = -1,
> + Â Â Â Â Â Â Â [ C(RESULT_MISS) Â ] = -1,
> + Â Â Â },
> + Â Â Â [ C(OP_PREFETCH) ] = {
> + Â Â Â Â Â Â Â [ C(RESULT_ACCESS) ] = -1,
> + Â Â Â Â Â Â Â [ C(RESULT_MISS) Â ] = -1,
> + Â Â Â },
> + },
> + [ C(BPU ) ] = {
> + Â Â Â [ C(OP_READ) ] = {
> + Â Â Â Â Â Â Â [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
> + Â Â Â Â Â Â Â [ C(RESULT_MISS) Â ] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
> + Â Â Â },Signed-off-by: Lin Ming <ming.m.lin@xxxxxxxxx>
> + Â Â Â [ C(OP_WRITE) ] = {
> + Â Â Â Â Â Â Â [ C(RESULT_ACCESS) ] = -1,
> + Â Â Â Â Â Â Â [ C(RESULT_MISS) Â ] = -1,
> + Â Â Â },
> + Â Â Â [ C(OP_PREFETCH) ] = {
> + Â Â Â Â Â Â Â [ C(RESULT_ACCESS) ] = -1,
> + Â Â Â Â Â Â Â [ C(RESULT_MISS) Â ] = -1,
> + Â Â Â },
> + },
> +};
> +
> Âstatic __initconst const u64 westmere_hw_cache_event_ids
> Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â[PERF_COUNT_HW_CACHE_MAX]
> Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â[PERF_COUNT_HW_CACHE_OP_MAX]
> @@ -1062,6 +1162,17 @@ static __init int intel_pmu_init(void)
> Â Â Â Â Â Â Â Âpr_cont("Westmere events, ");
> Â Â Â Â Â Â Â Âbreak;
>
> + Â Â Â case 42: /* SandyBridge */
> + Â Â Â Â Â Â Â memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
> + Â Â Â Â Â Â Â Â Â Â Âsizeof(hw_cache_event_ids));
> +
> + Â Â Â Â Â Â Â intel_pmu_lbr_init_nhm();
> +
> + Â Â Â Â Â Â Â x86_pmu.event_constraints = intel_snb_event_constraints;
> + Â Â Â Â Â Â Â x86_pmu.enable_all = intel_pmu_nhm_enable_all;

I don't see the errata that would justify using the Nehalem workaround
enable_all
function here.
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