RE: [PATCHv1 09/12] unicore32 core architecture: timer and time

[Guan Xuetao]

> -----Original Message-----
> From: johnstul.lkml@xxxxxxxxx [mailto:johnstul.lkml@xxxxxxxxx] On Behalf Of john stultz
> Sent: Tuesday, December 28, 2010 5:27 AM
> To: Guan Xuetao
> Cc: linux-arch@xxxxxxxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx
> Subject: Re: [PATCHv1 09/12] unicore32 core architecture: timer and time
> 
> 2010/12/25 Guan Xuetao <guanxuetao@xxxxxxxxxxxxxxx>:
> > From: Guan Xuetao <guanxuetao@xxxxxxxxxxxxxxx>
> >
> > Patch 9 implements timer and time. RTC and PWM device drivers are also here.
> >
> > Signed-off-by: Guan Xuetao <guanxuetao@xxxxxxxxxxxxxxx>
> 
> Just a small request:
> 
> > +static struct clocksource cksrc_puv3_oscr = {
> > +       .name           = "oscr",
> > +       .rating         = 200,
> > +       .read           = puv3_read_oscr,
> > +       .mask           = CLOCKSOURCE_MASK(32),
> > +       .shift          = 18,
> 
> Drop the shift assignment here.
> 
> > +       cksrc_puv3_oscr.mult =
> > +               clocksource_hz2mult(CLOCK_TICK_RATE, cksrc_puv3_oscr.shift);
> > +
> Drop the mult assignment here.
> 
> 
> > +       clocksource_register(&cksrc_puv3_oscr);
> 
> Use "clocksource_register_hz(&cksrc_puv3_oscr, CLOCK_TICK_RATE );" and
> the kernel will fill in mult/shift appropriately.
> 
> If you have any troubles after doing so, let me know.

When using clocksource_register_hz(&cksrc_puv3_oscr, CLOCK_TICK_RATE ),
 the shift value become 0, and mult value become 0x838a91a7, and the system will be broken
after printing "Switching to clocksource oscr".

When using clocksource_register_khz(&cksrc_puv3_oscr, CLOCK_TICK_RATE ),
the shift value become 0, and mult value become  0x4359611, and the system will run smoothly,
but timer interrupt seems too frequently. Perhaps it is 4 times faster.

For comparison, originally, when shift value is set to 0x12, the mult value become 1175e5e.

Which one is better?

> 
> thanks
> -john

Thanks john.

Guan Xuetao


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