Re: [RFC PATCH 2/3 v3] perf: Implement Nehalem uncore pmu

[Stephane Eranian]

On Thu, Dec 9, 2010 at 9:19 PM, Peter Zijlstra <a.p.zijlstra@xxxxxxxxx> wrote:
> On Thu, 2010-12-09 at 21:15 +0100, Stephane Eranian wrote:
>> On Thu, Dec 9, 2010 at 8:21 PM, Peter Zijlstra <a.p.zijlstra@xxxxxxxxx> wrote:
>> > On Thu, 2010-12-02 at 13:20 +0800, Lin Ming wrote:
>> >> + Â Â Â /* Check CPUID signatures: 06_1AH, 06_1EH, 06_1FH */
>> >> + Â Â Â family = boot_cpu_data.x86;
>> >> + Â Â Â model = boot_cpu_data.x86_model;
>> >> + Â Â Â if (family != 6 || (model != 0x1A && model != 0x1E && model != 0x1F))
>> >> + Â Â Â Â Â Â Â return;
>> >
>> > So that's 26, 30 and 31? Curiously
>> > arch/x86/kernel/cpu/perf_event_intel.c does have 31.
>
> That was clearly meant to say: doesn't.. Does Intel have an exhaustive
> model list somewhere?
>
>> It is also missing model 44 (0x2c).
>
Uncore logic in the same on NHM and WSM.
Events may be different but I have not see a
public document that describes that.

> Right.. but if the westmere uncore is the same, then its also missing
> 37.
>
yes, 37 is also missing.

> The -EX chips have a different uncore, right?
>
True. I don't know if the programming is completely different
but it would not surprise me.
Documentation is at:
http://www.intel.com/assets/en_US/pdf/designguide/323535.pdf
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