Re: [PATCH] wrong PERF_COUNT_HW_CACHE_REFERENCES andPERF_COUNT_HW_CACHE_MISSES for AMD

[Stephane Eranian]

Robert,

Has there been any progress on this issue?

On Tue, Nov 2, 2010 at 12:08 PM, Robert SchÃne
<robert.schoene@xxxxxxxxxxxxx> wrote:
>
> >
> Yes, we could use event 4E1 (L3 Cache Misses), but we would need
> different event IDs for the different AMD Families. Not all of them have
> an L3-Cache and even some implementations of Family 10h don't have L3
> either.

I think you could introduce several generic event mapping tables, like what is
done for the various Intel processors, i.e., have variations of the
amd_perfmon_event_map[] table. Then, the kernel would auto-detect the
host CPU and pick the correct table. Same thing would have to be done
for the LL generic cache events if some mappings use Northbridge events.

In general, however, I would recommend not using those generic cache
events to begin with. I think you understand why now. When dealing with
PMU events, you should read the documentation first. Micro-architectures
vary greatly even within the same processor family.
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@xxxxxxxxxxxxxxx
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/