Re: intel_cacheinfo: potential NULL dereference?

From: Borislav Petkov
Date: Tue Jun 22 2010 - 09:07:13 EST


From: Jiri Slaby <jirislaby@xxxxxxxxx>
Date: Tue, Jun 22, 2010 at 07:20:14AM -0400

> On 06/22/2010 01:18 PM, Jiri Slaby wrote:
> > Hi,
> >
> > commit 9350f982 changed the code so it looks like:
> > static ssize_t store_cache_disable(struct _cpuid4_info *this_leaf,
> > const char *buf, size_t count,
> > unsigned int slot)
> > {
> > struct pci_dev *dev = this_leaf->l3->dev; <<1>>
> > int cpu = cpumask_first(to_cpumask(this_leaf->shared_cpu_map));
> > unsigned long val = 0;
> >
> > #define SUBCACHE_MASK (3UL << 20)
> > #define SUBCACHE_INDEX 0xfff
> >
> > if (!this_leaf->l3 || !this_leaf->l3->can_disable) <<2>>
> > return -EINVAL;
> >
> > Stanse found, that this_leaf->l3 is dereferenced at <<1>>, but checked
> > for being NULL at <<2>>. Is the check superfluous or the dev assignment
> > should go after the check?
>
> Oh, and I have another report with same symptoms for show_cache_disable.

Right, so I have a patch in tip/x86/cpu
(8cc1176e5de534d55cb26ff0cef3fd0d6ad8c3c0) which reorganizes
and cleans up that code. With it, all possible checks land in
amd_check_l3_disable() and if they have all been passed, the PCI dev is
guaranteed to be properly set. So no need for sprinkling additional NULL
checks in the code.

How's that?

--
Regards/Gruss,
Boris.

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