Re: [PATCH 4/5] kgdb: Use atomic operators which use barriers

[Linus Torvalds]

On Fri, 2 Apr 2010, Jason Wessel wrote:
> 
> Russell had this thread: 
> http://permalink.gmane.org/gmane.linux.ports.arm.kernel/75717

Russell is wrong.

Yes, originally it was about P4's overheating. But let me repeat: the fact 
is, this _is_ valid kernel code:

	kernel/sched.c-		while (task_is_waking(p))
	kernel/sched.c:			cpu_relax();

(where that "task_is_waking()" is simply doing two regular reads, and 
expects another CPU to be changing them).

This has _nothing_ to do with memory barriers, or with overheating. 

The fact that maybe some ARM6 cache coherency implementation is pure and 
utter sh*t and never sees the changes without the same instruction that 
happens to be a memory barrier on that architecture does not make that 
cpu_relax() any more about memory barriers.

Similarly, the fact that P4's wanted cpu_relax() in order to not overheat 
and cause slowdowns has _nothing_ to do with anything. 

All that matters is that the above kind of while loop must work. The 
architecture needs to do whatever it needs to do to make it work. End of 
discussion. If on ARM6 that means "smp_mb()", then that's an ARM6 
implementation issue.

		Linus
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