Re: [PATCH 1/5] x86-32: Split cache flush handler from simd handler

[H. Peter Anvin]

On 03/19/2010 09:08 PM, Brian Gerst wrote:
>>
>> Does anyone have *any idea* what processor this applies to?  I've
>> tracked the code back all the way to the original inclusion in the
>> kernel, and there isn't even the slightest hint.
>>
>> The comment, of course, is a great example on how *not* to write
>> comments... it should have mentioned the CPU in question.
> 
> This thread appears to describe the problem:
> http://marc.info/?t=104960872800014&r=1&w=2
> 
> And the initial patch:
> http://marc.info/?l=linux-kernel&m=104960870106838&w=2
> 
> It looks like to me, that an AMD 486 clone has an erratum where the
> invd instruction from userspace generates exception 19 (13 hex)
> instead of #GP (13 dec).
> 

Ah, guess it was even older than I first realized ... I should have
searched for the string "cache flush denied" instead.

Sounds like we should do three things:

a) update the comment to actually reflect what is going on;
b) compile it out for > 486;
c) report the error as trap 13 rather than 19.

	-hpa

-- 
H. Peter Anvin, Intel Open Source Technology Center
I work for Intel.  I don't speak on their behalf.

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