Re: USB mass storage and ARM cache coherency

[Alan Stern]

On Tue, 2 Feb 2010, Oliver Neukum wrote:

> Am Dienstag, 2. Februar 2010 13:39:35 schrieb Catalin Marinas:
> > > For storage that is correct. But what about other sources of pages,
> > > for example iSCSI?
> > 
> > In the iSCSI case, does the HCD driver write directly to a page cache
> > page? Or it just fills in network packets that are copied to page cache
> > pages by the iSCSI code (sorry, I'm not familiar with this part of the
> > kernel). If the latter, the cache flushing in the HCD driver would not
> > help and it needs to be done in the iSCSI code.
> 
> As far as I can tell iSCSI does a private copy. But I don't know how
> many methods to transfer code pages over USB exist. I'd say the
> conservative solution is to flush for everything but control transfers.

This doesn't make any sense.  Nobody would ever use isochronous 
transfers to store data into a code page because isochronous is 
unreliable.  (Audio isn't a counterexample -- audio data may be mapped 
to userspace, but only to data pages, not code pages.  And the problem 
here is to maintain consistency between the D and I caches.)

In principle interrupt transfers could be used, but it is most
unlikely.  They are intended for bounded-latency transfers, not
transfers of potentially large amounts of data.

The only transfer type that makes sense to worry about is bulk.

Alan Stern

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