Re: [patch] cache-miss and cache-refs events on P6-mobile CPUs
From: Peter Zijlstra
Date: Tue Aug 11 2009 - 08:05:59 EST
On Tue, 2009-08-11 at 11:34 +0200, Ingo Molnar wrote:
> @@ -116,8 +116,8 @@ static const u64 p6_perfmon_event_map[]
> {
> [PERF_COUNT_HW_CPU_CYCLES] = 0x0079,
> [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
> - [PERF_COUNT_HW_CACHE_REFERENCES] = 0x0000,
> - [PERF_COUNT_HW_CACHE_MISSES] = 0x0000,
> + [PERF_COUNT_HW_CACHE_REFERENCES] = 0x0f2e,
> + [PERF_COUNT_HW_CACHE_MISSES] = 0x012e,
2e is total numer of L2 events,
0f is all mesi states
01 is invalid states
Yes they are numbers, but no they are not full cache refs and misses.
I don't think this is a good patch.
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