[PATCH 0/3 v2] x86: adapt CPU topology detection for AMDMagny-Cours

[Andreas Herrmann]

Hi,

Second attempt to fix CPU topology representation for multi-node
processors.

Using topology information from /sys/devices/system/cpu/cpu*/topology
you can identify

 phys_package by physical_package_id
 core         by core_id + physical_package_id

Corresponding sibling information is

  Level        | Set of CPUs
 --------------|---------------
  phys_package | core_siblings
  core         | thread_siblings
  thread       | one CPU

Example:

  cpu19: physical_package_id        : 1
  cpu19: core_id                    : 7
  cpu19: thread_siblings            : 00080000
  cpu19: thread_siblings_list       : 19
  cpu19: core_siblings              : 00fff000
  cpu19: core_siblings_list         : 12-23

I am adding cpu_node_id, cpu_node_siblings, cpu_node_siblings_list
to get the complete hierarchy. Now you can identify

 phys_package by physical_package_id
 cpu_node     by physical_package_id + cpu_node_id
 core         by physical_package_id + cpu_node_id + core_id

In contrast to first patch set I don't change the meaning of
core_siblings. Thus we have following sets of CPUs on a socket

  Level        | Set of CPUs
 --------------|---------------
  phys_package | core_siblings
  cpu_node     | cpu_node_siblings
  core         | thread_siblings
  thread       | one CPU

Example:

  cpu19: physical_package_id        : 1
  cpu19: core_id                    : 1
  cpu19: thread_siblings            : 00080000
  cpu19: thread_siblings_list       : 19
  cpu19: cpu_node_id                : 0
  cpu19: cpu_node_siblings          : 00fc0000
  cpu19: cpu_node_siblings_list     : 18-23
  cpu19: core_siblings              : 00fff000
  cpu19: core_siblings_list         : 12-23

The cpu_node level information is stored in struct cpuinfo_x86.cpu_node_id
and in cpu_node_map. It can be accessed using topology_cpu_node_id(cpu)
and topology_cpu_node_cpumask(cpu).

Note:
 A cpu_node is a functional unit. In case of AMD Magny-Cours it
 contains a number of cores, configuration registers, memory
 controler, ... A cpu_node is _not_ necessarily a NUMA node.

 If you doubt this. Think of node interleaving where strictly speaking
 you have no NUMA but spread memory accesses across all nodes
 (depending on some bits of the memory address).  The NUMA node
 topology is provided via ACPI tables (e.g. SRAT, SLIT). The contents
 of such tables might vary with different BIOS settings - the CPU
 topology is constant.

Patches are against tip/master.
Please apply.


Thanks,
Andreas

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