Re: [PATCH -tip 3/6 V4.1] x86: instruction decorder API

[Jim Keniston]

On Tue, 2009-04-21 at 20:17 -0400, Masami Hiramatsu wrote:
...
> Hi Peter and Jim,
> 
> Now what I'm doing is making opcode tables like this.
> 
> Table: 1-byte opcode
> Alias: none
> 00: ADD Eb,Gb
> 01: ADD Ev,Gv
> 02: ADD Gb,Eb
> 03: ADD Gv,Ev
> 04: ADD AL,Ib
> 05: ADD rAX,Iz
> 06: PUSH ES (i64)
> 07: POP ES (i64)
> 08: OR Eb,Gb
> 09: OR Ev,Gv
> 0a: OR Gb,Eb
> 0b: OR Gv,Ev
> 0c: OR AL,Ib
> 0d: OR rAX,Iz
> 0e: PUSH CS
> 0f: 2-byte escape
> ...

We want to keep this info easy to parse. (Who knows how it might be
used, and by whom?)  Your format seems to be
	opcode: mnemonic [comma,separated,operands] [(extra_info)]
which is fine if you stick to it... but your entry for 0f doesn't match
that.

Also, something like
	+ extra_info
would be easier to parse (using, say, awk) than
	(extra_info)

> 
> and a parser script which parses them into,
> 
> const insn_attr_t primary_table[INAT_TABLE_SIZE] = {
> 	[0x04] = INAT_IMM(IMM_SIZE_BYTE)
> 	[0x05] = INAT_IMM(IMM_SIZE_VWORD32)
> 	[0x0c] = INAT_IMM(IMM_SIZE_BYTE)
> 	[0x0d] = INAT_IMM(IMM_SIZE_VWORD32)
> 	[0x0f] = INAT_ESC(IMM_ESC_2BYTE)
> ...
> 
> (note, instructions which has no attributes for decoder, are just ignored)
> 
> 
> By the way, I'm worried about legal things of Intel's instruction
> encoding expressions. Would you think there is any problem if we
> have those tables in the kernel tree?

Good question.  Sorry, I'm not a lawyer.  Intel and AMD and sandpile.org
all seem to be using the same notation, so the notation's inventor must
not be feeling too proprietary.  Interestingly, sandpile.org asserts a
copyright.

> 
> Thanks,
> 

Jim

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