Re: [PATCH -tip 3/6 V4.1] x86: instruction decorder API

[Jim Keniston]

On Thu, 2009-04-16 at 19:31 -0400, Masami Hiramatsu wrote:
...
> 
> Hmm, I have an idea about instruction table. Usually, instruction tables
> are encoded with code defined by each decoder/emulator. This method
> will show their internal code directly, and is hard to maintain when
> the opcode map is updated. Instead of that, I'd like to suggest using
> the expressions in the opcode maps in a vender's genuine document (in
> this case, Intel/AMD's manual) or www.sandpile.org for instruction
> tables.
> 
> e.g.
> 
> const insn_attr_t onebyte_attr_table[ATTR_TABLE_SIZE] = {
> /* 0x00-0x0f */
> AT2(Eb,Gb), AT2(Ev,Gv),  AT2(Gb,Eb),  AT2(Gv,Ev),
> AT2(AL,Ib), AT2(rAX,Iz), AT2(ES,i64), AT2(ES,i64),
> AT2(Eb,Gb), AT2(Ev,Gv),  AT2(Gb,Eb),  AT2(Gv,Ev),
> AT2(AL,Ib), AT2(rAX,Iz), AT2(CS,i64), AT(ESC),
> ...
> 
> Here, AT and AT2 macros are defined as follows:
> 
> #define AT(a) (INAT_OMEXP_##a)
> #define AT2(a1, a2) (INAT_OMEXP_##a1 | INAT_OMEXP_##a2)
> 
...

It looks like AT2(Ev,Gv) would yield the same bits as AT2(Gv,Ev).  It'd
be nice not to lose the operand-order information.  And we'd have to
make clear whether which notation we're using -- src,dest as in the gnu
assembler, or dest,src as in the AMD (and Intel?) manuals.

Jim

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