Re: PAGE_CACHE_WC strikes again

[Jesse Barnes]

On Tue, 31 Mar 2009 17:03:10 -0800
Suresh Siddha <suresh.b.siddha@xxxxxxxxx> wrote:

> On Tue, 2009-03-31 at 17:29 -0700, Pallipadi, Venkatesh wrote:
> > The key point here is 
> > 
> > > setting PAGE_CACHE_WC disables the WC effect of the
> > > MTRR on my non-PAT (disabled due to CPU errata)
> > 
> > When PAT is disabled, the default setting in PAT MSR is
> > 00 - WB
> > 01 - WT
> > 10 - UC_MINUS
> > 11 - UC
> > 
> > There is no way to set WC with PAT. By hardcoding _PAGE_CACHE_WC
> > (which is 01) the driver is basically selecting write-through!
> > 
> > And when MTRR says WC and PAT says WT, effective type is UC.
> > 
> > Basically, no one should be hard-coding the memory type. Please use
> > pgprot_writecombine() which does the right thing by using WC
> > (when PAT is enabled) or UC_MINUS (when PAT is disabled).
> 
> And the driver should use right API to track the underlying page frame
> thats getting mapped by this vma, with the corresponding attribute.
> API's like remap_pfn_range(), vm_insert_pfn() will setup the PTE's
> aswell as track the pfn's attributes.
> 
> API's like set_memory_uc/wc() will explicitly setup the page
> attributes.
> 
> Jesse, As far as I see, the drm GEM fault handler routines don't seem
> to do any of this. Am I missing something? We need to fix this so
> that we can avoid potential aliasing issues.

Right, the drm driver code went in before we had pgprot_writecombine.
Now that it's available we should definitely use it.  I'm not sure
about the set_memory_* routines though; we create io mappings in
i915_dma.c at init time, and I thought we took care of things in
i915_gem.c but we may need updates there.

-- 
Jesse Barnes, Intel Open Source Technology Center
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