RE: PAGE_CACHE_WC strikes again

[Pallipadi, Venkatesh]

>-----Original Message-----
>From: Jesse Barnes [mailto:jbarnes@xxxxxxxxxxxxxxxx] 
>Sent: Tuesday, March 31, 2009 5:15 PM
>To: Eric Anholt
>Cc: lkml; Pallipadi, Venkatesh
>Subject: Re: PAGE_CACHE_WC strikes again
>
>On Tue, 31 Mar 2009 17:10:47 -0700
>Eric Anholt <eric@xxxxxxxxxx> wrote:
>
>> I just tracked down what was cutting performance 10x on one of my
>> systems on a microbenchmark I'd just written:
>> 
>> --- a/drivers/gpu/drm/drm_gem.c
>> +++ b/drivers/gpu/drm/drm_gem.c
>> @@ -540,7 +540,7 @@ int drm_gem_mmap(struct file *filp, struct
>> vm_area_struct *vma)
>>  	/* FIXME: use pgprot_writecombine when available */
>>  	prot = pgprot_val(vma->vm_page_prot);
>>  #ifdef CONFIG_X86
>> -	prot |= _PAGE_CACHE_WC;
>> +	/*prot |= _PAGE_CACHE_WC;*/
>>  #endif
>>  	vma->vm_page_prot = __pgprot(prot);
>>  
>> Turns out that setting PAGE_CACHE_WC disables the WC effect of the
>> MTRR on my non-PAT (disabled due to CPU errata) 945GM 
>system, and this
>> workaround took GTT-mapped writes from 120MB/s to 1180MB/s.
>
>What the...  There's a pgprot_writecombine now, but it basically does
>the same thing.  Why is WC so broken?  Venki is the fix for this
>covered in your last patchset?
>

The key point here is 

> setting PAGE_CACHE_WC disables the WC effect of the
> MTRR on my non-PAT (disabled due to CPU errata)

When PAT is disabled, the default setting in PAT MSR is
00 - WB
01 - WT
10 - UC_MINUS
11 - UC

There is no way to set WC with PAT. By hardcoding _PAGE_CACHE_WC
(which is 01) the driver is basically selecting write-through!

And when MTRR says WC and PAT says WT, effective type is UC.

Basically, no one should be hard-coding the memory type. Please use
pgprot_writecombine() which does the right thing by using WC
(when PAT is enabled) or UC_MINUS (when PAT is disabled).

Thanks,
Venki--
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