Re: [PATCH 1/5]: drm: ati_pcigart: Do not access I/O MEM spaceusing pointer derefs.

[David Miller]

From: Benjamin Herrenschmidt <benh@xxxxxxxxxxxxxxxxxxx>
Date: Sat, 14 Feb 2009 20:07:54 +1100

> > I did some research, and it does appear that the GART does read the
> > PTEs from the VRAM using the Host Data Path.  This means the surface
> > control byte swapping settings are applied.
> > 
> > So for depths of 16 and 24, the GART is reading garbage PTEs.  And
> > that's why the CP hangs.
> 
> That makes me wonder how the heck did it work for me ! Or maybe... I've
> been using an R5xx which happens to have a bit that I haven't seen on
> R3xx that allows ... to set whether the GART reads come from HDP or
> directly from MC. That might be what saved my ass here.

I wonder.  But I really doubt it.  The bit is off by default
and the radeon DRM code explicitly sets it to off.

> We can do that by registering a surface from the kernel to cover the
> GART I suppose, and clean things a bit so that when using the DRI, X
> doesn't touch the surface registers -at all- and leaves it to the
> kernel.

That actually sounds like a good idea.
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