Re: [RFC PATCH crypto] AES: Add support to Intel AES-NI instructions

[Herbert Xu]

Huang Ying <ying.huang@xxxxxxxxx> wrote:
>
> f. if TS is clear, then use x86_64 implementation. Otherwise if
> user-space has touched the FPU, we save the state, if not then simply
> clear TS.

Well I'd rather avoid using the x86_64 implementation ever because
unless the chip guys have really screwed up we should be looking at
a difference of at least a factor of 10.

BTW I wasn't very clear in the original email.  You'd only do the
asynchronous operation for CBC/ECB.  For the simple AES case I
suppose we'll just have to stick to the x86_64 fallback.  This'll
really suck for disk encryption but I guess you could always add
an LRW/XTS mode to your code.

Cheers,
-- 
Visit Openswan at http://www.openswan.org/
Email: Herbert Xu ~{PmV>HI~} <herbert@xxxxxxxxxxxxxxxxxxx>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@xxxxxxxxxxxxxxx
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/